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Assistant Professor Departments of Electrical Engineering and Computer Science Stanford University
Address: Gates Building, Room 333 353 Serra Mall, Stanford, CA 94305
Email: subh at stanford dot edu Phone: 650-724-1915
Admin: Uma Mulukutla Email: uma at cs dot stanford dot edu Office: Gates Building, Room 303 Phone: 650-725-3726 Fax: 650-725-6949
Research interests: Robust system design, VLSI design, CAD, validation & test, computer architecture, design for emerging nanotechnologies |
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Biography: Subhasish Mitra is an Assistant Professor in the Departments of Electrical Engineering and Computer Science of Stanford University where he leads the Stanford Robust Systems Group. His research interests include: 1. Robust system design; 2. VLSI design, CAD, validation and test; 3. Design for emerging nanotechnologies. Prior to joining Stanford, Prof. Mitra was a Principal Engineer at Intel Corporation. He received Ph.D. in Electrical Engineering from Stanford University.
Prof. Mitra has co-authored 100+ technical papers, and has invented design and test techniques that have seen wide-spread proliferation in the semiconductor industry. His X-Compact technique for test compression is used by 50+ Intel products, and is supported by major CAD tools. His work on imperfection-immune circuits using carbon nanotubes, jointly with his students and collaborators, has been highlighted by the MIT Technology Review, Semiconductor Research Corporation, EE Times, and several others.
Prof. Mitra's major honors include the Presidential Early Career Award for Scientists and Engineers (PECASE, the highest honor bestowed by the US government on early career outstanding scientists and engineers), National Science Foundation CAREER Award, Terman Fellowship, IEEE Circuits and Systems Society Donald O. Pederson Award for the best paper published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ACM SIGDA Outstanding New Faculty Award, Best Paper Award at the IEEE/ACM Design Automation Conference, a Divisional Recognition Award from Intel “for a Breakthrough Soft Error Protection Technology,” a Best Paper Award at the Intel Design and Test Technology Conference for his work on Built-In Soft Error Resilience, and the Intel Achievement Award, Intel’s highest corporate honor, “for the development and deployment of a breakthrough test compression technology.” |
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