Tutorials:

  1. S. Mitra and P. Sanda, “Soft Errors: System Effects, Protection Techniques and Case Studies,” International Conf. Dependable Systems and Networks, 2008.

  2. S. Mitra, P. Sanda, and N. Seifert, “Soft Errors: Technology Trends, System Effects and Protection Techniques,” IEEE VLSI Test Symposium, 2008.

  3. S. Mitra, P. Sanda, and N. Seifert, “Soft Errors: Technology Trends, System Effects and Protection Techniques,” International On-line Test Symposium, 2008.

  4. S. Mitra and P. Sanda, “Soft Errors: System Effects, Protection Techniques and Case Studies,” Design Automation and Test in Europe, 2008.

  5. S. Mitra, P. Sanda, and A. Lesea, “Soft Errors: Technology Trends, System Effects and Protection Techniques,” Design Automation Conference, 2007.

  6. S. Mitra, P. Sanda, and N. Seifert, “Soft Errors: Technology Trends, System Effects and Protection Techniques,” International On-line Test Symposium, 2007.

  7. S. Mitra, P. Sanda, and N. Seifert, “Soft Errors: Technology Trends, System Effects and Protection Techniques,” International Test Conference, 2006.

  8. S. Mitra, L. Spainhower, V. Narayanan and Y. Xie, “Robust System Design from Unreliable Components,” International Symposium on Computer Architecture, 2005.

  9. S. Mitra and S. Blanton, “Testing Nanometer Integrated Circuits: Myths, Reality and the Road Ahead,” IEEE Intl. Conf. VLSI Design, 2005.

  10. S. Mitra, “Robust System Design,” Hotchips, 2003.

Book Chapters:

  1. S. Mitra, M. Zhang, N. Seifert, T.M. Mak and K.S. Kim “Soft Error Resilient System Design through Error Correction,” Springer, 2007 (Invited).

  2. E.J. McCluskey and S. Mitra, “Fault-Tolerance,” Encyclopedia on Computer Science and Engineering, CRC Press, 2004 (Invited).

Journal Publications:

  1. N. Shanbhag, S. Mitra, G. de Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, J. Rabaey , “In Search of Alternative Computational Paradigms,” IEEE Design and Test of Computers, 2008.

  2. R. Kapur, S. Mitra, and T.W. Williams, “Historical Perspective of Scan Compression,” IEEE Design and Test of Computers, 2008 (Invited).

  3. M. Zhang, S. Mitra, TM Mak, N. Seifert, Q. Shi, K.S. Kim, N. Shanbhag, N. Wang and S.J. Patel, “Sequential Element Design with Built-In Soft Error Resilience,” IEEE Trans. VLSI, Dec. 2006.

  4. M. Tahoori and S. Mitra, “Application-Dependent Delay Testing of FPGAs,” IEEE Trans. CAD, 2006.

  5. S. Mitra, N. Seifert, M. Zhang, Q. Shi and K.S. Kim, “Robust System Design with Built-In Soft Error Resilience,” IEEE Computer, Vol. 38, Number 2, pp. 43-52, Feb. 2005.

  6. S. Mitra and K.S. Kim, “XPAND: An Efficient Test Stimulus Compression Technique,” IEEE Trans. Computers, Special Issue on System-on-Chip Design and Test, 2006.

  7. S. Mitra, S. Lumetta, M. Mitzenmacher and N. Patil, “X-Tolerant Test Response Compaction,” IEEE Design and Test of Computers, Special Section on the 2005 International Test Conference, Nov.-Dec. 2005.

  8. R.K. Iyer, N. Nakka, Z. Kalbarczyk and S. Mitra, “Recent Advances in Hardware-Level Reliability Support for Transient Errors,” IEEE MICRO, Special Issue on the Reliability-Aware Microarchitectures, Nov.-Dec. 2005.

  9. M. Tahoori and S. Mitra, “Application Independent Testing of FPGA Interconnects,” IEEE Trans. CAD, Nov. 2005.

  10. Al-Yamani, S. Mitra and E.J. McCluskey, “Optimized Reseeding by Seed Ordering and Encoding,” IEEE Trans. CAD, Feb. 2005.

  11. S. Mitra, W. Huang. N.R. Saxena, S. Yu and E.J. McCluskey, “Reconfigurable Architecture for Autonomous Self-Repair,” IEEE Design & Test of Computers, Special Issue on Yield & Reliability, Vol. 21, Issue 3, pp. 228-240, May-June 2004.

  12. S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique,” IEEE Trans. Computer-Aided Design, Vol. 23, Issue 3, pp. 421-432, March 2004.

  13. S. Mitra, N.R. Saxena, and E.J. McCluskey, “Efficient Design Diversity Estimation for Combinational Circuits,” IEEE Trans. Comp., Vol. 53, Issue 11, pp. 1,483-1,492, Nov. 2004.

  14. S. Mitra, W. Huang, N. Saxena, S. Yu, E.J. McCluskey, “Dependable Reconfigurable Systems: Reliability Obtained by Adaptive Re-configuration,” ACM Trans. Embedded Computing Systems, to appear.

  15. M. Tahoori and S. Mitra, “Techniques and Algorithms for Fault Grading of FPGA Interconnect Test Configurations,” IEEE Trans. Computer-Aided Design, Vol. 23, Issue 2, pp. 261-272, Feb. 2004.

  16. N.R. Saxena, S. Mitra, C. Zeng and E.J. McCluskey, “Concurrent Error Detection in Reconfigurable Systems – New Opportunities,” IEEE Design and Test of Computers, to appear.

  17. K.S. Kim, S. Mitra and P.G. Ryan, “Delay Defect Characteristics and Testing Strategies,” IEEE Design and Test of Computers, Special Issue on Speed Test and Speed Binning of Complex ICs, Vol. 20, Issue 5, pp. 8-16, Sept.-Oct. 2003.

  18. S. Mitra, N.R. Saxena and E.J. McCluskey, “A Design Diversity Metric and Analysis of Redundant Systems,” IEEE Trans. Computers, Vol. 51, Issue 5, pp. 498-510, May 2002.

  19. N.S. Oh, S. Mitra and E.J. McCluskey, “ED4I: Error Detection by Diverse Data and Duplicated Instructions,” IEEE Trans. on Computers, Special Issue on Fault-Tolerant Embedded Systems, Vol. 51, Issue 2, pp. 180-199, Feb. 2002.

  20. S. Mitra, N.R. Saxena and E.J. McCluskey, “Common-Mode Failures in Redundant VLSI Systems: A Survey,” IEEE Trans. Reliability, Special Issue on Fault-Tolerant VLSI Systems, Vol. 49, Issue 3, pp. 285-295, Sept. 2000.

  21. S. Mitra, L.J. Avra and E.J. McCluskey, “Efficient Multiplexer Synthesis,” IEEE Design and Test of Computers, Vol. 17, No. 4, pp. 90-97, Oct. – Dec. 2000.

  22. N.R. Saxena, S. Gomez, W. Huang, S. Mitra, S. Yu and E.J. McCluskey, “Dependable Computing and On-Line Testing in Adaptive and Reconfigurable Systems,” IEEE Design and Test of Computers, Special Issue on Reconfigurable Computing, Vol. 17, No. 1, pp. 29-41, Jan. – Mar. 2000.

  23. S. Mitra, L.J. Avra and E.J. McCluskey, “An Output Encoding Problem and a Solution Technique,” IEEE Trans. Computer-Aided Design, Vol. 18, No. 6, pp. 761-768, June 1999.

Conference Publications:

  1. N. Patil, A. Lin, E. Myers, H.S.-P. Wong and S. Mitra, “Integrated Wafer-scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures,” 2008 Symp. VLSI Technology, 2008.

  2. S. Park and S. Mitra, “IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Bug Localization in Processors,” IEEE/ACM Design Automation Conf., 2008.

  3. T.W. Chen, K. Kim, Y. Kim and S. Mitra, “Gate-Oxide Early Life Failure Prediction,” IEEE VLSI Test Symp., 2008.

  4. Y. Li, S. Makar and S. Mitra, “CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns,” Design Automation and Test in Europe, 2008.

  5. J. Zhang, N. Patil and S. Mitra, “Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Circuits,” Design Automation and Test in Europe, 2008.

  6. S. Mitra, “ Globally Optimized Robust Systems to Overcome Scaled CMOS Challenges,” Design Automation and Test in Europe, 2008 (Invited).

  7. S. Mitra, “Circuit Failure Prediction for Robust System Design in Scaled CMOS,” International Reliability Physics Symp., 2008 (Invited).

  8. N. Patil, J. Deng, H.-S.P. Wong and S. Mitra, “Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits,” Design Automation Conference, 2007.

  9. S. Mitra and M. Agarwal, “Circuit Failure Prediction to Overcome Scaled CMOS Reliability Challenges,” Intl. Test Conf., 2007 (Invited).

  10. M. Agarwal, B. Paul and S. Mitra, “Circuit Failure Prediction and Its Application to Transistor Aging,” IEEE VLSI Test Symp., 2007.

  11. J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra and H.-S.P. Wong, “Carbon Nanotube Transistor Circuits: Circuit-level Performance Benchmarking and Design Options for Living with Imperfections,” Intl. Solid State Circuits Conf. (ISSCC), 2007.

  12. P. Relangi and S. Mitra, “Erratic Bit Errors in Latches,” Intl. Reliability Physics Symp. (IRPS), 2007.

  13. S. Seshia, W. Li and S. Mitra, “Verification Guided Soft Error Resilience,” Design Automation and Test in Europe (DATE), 2007.

  14. T.W. Chen, C. Ito, W. Loh, W. Wang, S. Mitra and R.W. Dutton, “Marco-model for Post-breakdown 90nm and 130nm Transistors and its Applications in Predicting Chip-level Function Failure after ESD-CDM Events,” Intl. Reliability Physics Symp., 2007.

  15. S. Mitra, M. Zhang, N. Seifert, TM Mak and K.S. Kim, “Built-In Soft Error Resilience for Robust System Design,” Intl. Conf. Integrated Circuit Design and Technology, 2007 (Invited).

  16. N. Patil, J. Deng, S. Mitra and H.-S.P. Wong, “Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits,” GomacTech, 2007 (Invited).

  17. K.Y. Cho, S. Mitra and E.J. McCluskey, “California Scan: A Scan Architecture to Utilize Don't Care Bits in Test Patterns,” Intl. Test Conf., 2007.

  18. B. Mungamuru, H. Garcia Molina, and S. Mitra, “How to Safeguard your Sensitive Data,” Intl. Symp. Reliable Distributed Systems, 2006.

  19. J. Deng, N.P. Patil, S. Mitra and H.S.P. Wong, “Designing Circuits with Carbon Nanotubes: Open Questions and Some Directions,” IEEE Nano, 2006 (Invited).

  20. S. Mitra, M. Zhang, N. Seifert, T.M. Mak, and K.S. Kim, “Soft Error Resilient System Design through Error Correction,” IFIP SOC VLSI, 2006 (Invited).

  21. S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas and K.S. Kim, “Combinational Logic Soft Error Correction,” IEEE Intl. Test Conf., 2006.

  22. N.P. Patil, S. Mitra and S.S. Lumetta, “Signature Analyzer Design for Yield Learning Support,” IEEE Intl. Test Conf., 2006.

  23. M. Tahoori and S. Mitra, “Test Compression for FPGAs,” IEEE Intl. Test Conf., 2006.

  24. N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra and J. Maiz, “Radiation Induced Soft Error Rates of Advanced CMOS Bulk Devices,” IEEE Intl. Reliability Physics Symp., 2006.

  25. R. Guo, S. Mitra, J. Lee, S. Sivaraj and M. Ameen, "Comparison of Test Metrics: Stuck-at, N-Detect and Gate-Exhaustive," IEEE VLSI Test Symp., 2006.

  26. S. Mitra, M. Zhang, T.M. Mak, N. Seifert, V. Zia and K.S. Kim, “Logic Soft Errors: A Major Barrier to Robust Platform Design,” Intl. Test Conf., 2005.

  27. D.J. Leavins, K.S. Kim, S. Mitra and E. Rodriguez, “Robust Platform Design in Sub-65nm Technologies,” Custom Integrated Circuits Conference, 2005, (Invited).

  28. Z. Stanojevic. R. Guo, S. Mitra and S. Venkataraman, “Enabling Yield Analysis with X-Compact,” Intl. Test Conf., 2005.

  29. K.Y. Cho, S. Mitra and E.J. McCluskey, “Gate Exhaustive Testing,” Intl. Test Conf., 2005.

  30. S. Mitra, T. Karnik, N. Seifert and M. Zhang, “Logic Soft Errors in Sub-65nm Technologies: Design and CAD Challenges,” Design Automation Conf., 2005.

  31. T.M. Mak, S. Mitra and M. Zhang, “DFT Assisted Built-In Soft Error Resilience,” IEEE Intl. On-line Test Symp., 2005, (Invited).

  32. S. Mitra, “Built-In Soft Error Resilience Techniques,” IEEE VLSI Test Symp., 2005, (Invited).

  33. S. Mitra, K.S. Kim, T.M. Mak, N. Seifert, P. Shipley, M. Zhang and V. Zia, “Built-In Soft Error Resilience Structures,” Intel Design and Test Technology Conference, 2005.

  34. Z. Stanojevic, R. Guo, S. Mitra and S. Venkataraman, “Fault Diagnosis with X-Compact,” Intel Design and Test Technology Conference, 2005.

  35. E. Volkerink and S. Mitra, “Test Response Compression with Any Number of Unknowns,” Design Automation Conference, 2005.

  36. S. Mitra, S. Lumetta and M. Mitzenmacher, “X-Tolerant Signature Analysis,” IEEE Intl. Test Conf., pp. 432-441, 2004.

  37. K. Brand, S.Mitra, E. Volkerink and E.J. McCluskey, “Speed Clustering of Integrated Circuits,” IEEE Intl. Test Conf., pp. 1128-1137, 2004.

  38. M. Tahoori and S. Mitra, “Interconnect Delay Testing of Designs on Programmable Logic Devices,” IEEE Intl. Test Conf., 2004.

  39. S. Mitra and K.S. Kim, “XPAND: Test Stimulus Compression for Intel Designs,” Intel Design and Test Technology Conf., 2004.

  40. P. Johnson, D. Wu, S. Mitra and S. Venkataraman, “Elimination of System Test from Production Test Flow,” Intel Quality and Reliability Technical Symp., 2004.

  41. S. Mitra and K.S. Kim, “Xpand + X-Compact: What did we Learn?”, IEEE VLSI Test Symp., 2004 (Invited).

  42. S. Mitra, E. Volkerink, E.J. McCluskey and S. Eichenberger, “Delay Defect Screening using Process Monitor Structures,” IEEE VLSI Test Symp., pp. 43-48, 2004.

  43. E.J. McCluskey, S. Mitra, et al., “ELF-MURPHY Data on Defects and Test Sets,” IEEE VLSI Test Symp., pp. 16-22, 2004.

  44. M. Tahoori and S. Mitra, “Defect and Fault Tolerance for Reconfigurable Molecular Computing,” IEEE Field Programmable Custom Computing Machines (FCCM), pp. 176-185, 2004.

  45. S. Mitra, H. Nguyen, N. Tam and K.S. Kim, “Soft Errors in Digital Logic,” Intel Quality and Reliability Technical Symp., 2003.

  46. S. Mitra and K.S. Kim, “XMAX: X-Tolerant Architecture for Maximal Test Compression,” IEEE Intl. Conf. Computer Design, pp. 326-330, 2003. (Invited)

  47. S. Lumetta and S. Mitra, “X-Codes: Error Control with Unknowable Inputs,” IEEE Intl. Symp. Information Theory, p. 102, 2003.

  48. D. Wu, M. Lin, S. Mitra, et al., “H-DFT: A Hybrid DFT Architecture for Low-Cost High Quality Structural Testing,” IEEE Intl. Test Conf., pp. 1229-1238, 2003.

  49. S. Mitra, S. Kallepalli and K.S. Kim, “Analysis of X-Compact for Intel ASIC Designs,” Intel Design and Test Technology Conf., 2003.

  50. S. Mitra, K.S. Kim and G.C. Parrish, “Design for Guaranteed Test Stimulus Compression,” Intel Design and Test Technology Conf., 2003.

  51. E. Volkerink and S. Mitra, “Efficient Seed Utilization for Reseeding based Compression,” IEEE VLSI Test Symp., pp. 232-237, 2003.

  52. M. Tahoori and S. Mitra, “Automatic Configuration Generation for FPGA Interconnect Testing,” IEEE VLSI Test Symp., pp. 134-139, 2003.

  53. A. Al Yamani, S. Mitra and E.J. McCluskey, “BIST Reseeding with Very Few Seeds,” IEEE VLSI Test Symp. , pp. 69-74, 2003.

  54. S. Mitra and K.S. Kim, “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” IEEE Intl. Test Conf., pp. 311-320, 2002.

  55. E. Volkerink, S. Mitra and A. Khoche, “Packet Based Test Vector Compression Techniques,” IEEE Intl. Test Conf., pp. 154-163, 2002.

  56. S. Mitra and K.S. Kim, “Efficient Response Compaction,” Intel Design and Test Technology Conf., July 2002.

  57. A. Khoche, S. Mitra and E. Volkerink, “Test Vector Compression using EDA-ATE Synergies,” IEEE VLSI Test Symp., pp. 97-102, 2002.

  58. S. Mitra and E.J. McCluskey, “Dependable Reconfigurable Computing: Design Diversity and Self-Repair,” NASA/DoD Intl. Conf. Evolvable Hardware, 2002. (Invited)

  59. M. Tahoori, S. Mitra and E.J. McCluskey, “Fault Grading FPGA Interconnect Test Configurations,” IEEE Intl. Test Conf., pp. 608-617, 2002.

  60. S. Mitra, E.J. McCluskey and S. Makar, “Design for Testability and Testing of IEEE 1149.1 TAP Controller,” IEEE VLSI Test Symp., pp. 247-252, 2002.

  61. A. Al-Yamani, S. Mitra, E.J. McCluskey, “Testing Digital Circuits with Constraints,” IEEE Intl. Symp. Defect Fault Tolerance, 2002.

  62. S. Mitra, N. Saxena and E.J. McCluskey, “Techniques for Estimation of Design Diversity for Combinational Logic Circuits,” IEEE Intl. Conf. Dependable Systems and Networks, pp. 25-34, 2001.

  63. S. Mitra and E.J. McCluskey, “Design Diversity for Concurrent Error Detection in Sequential Logic Circuits,” IEEE VLSI Test Symp., pp. 178-183, 2001.

  64. S. Mitra and E.J. McCluskey, “Design of Redundant Systems Protected Against Common-Mode Failures,” IEEE VLSI Test Symp., pp. 190-195, 2001.

  65. W-J. Huang, S. Mitra and E. J. McCluskey, “Fast Run-Time Fault Location for Dependable FPGA Applications,” IEEE Intl. Symp. Defect and Fault Tolerance, pp. 206-214, 2001.

  66. C.W. Tseng, S. Mitra, E.J. McCluskey and S. Davidson, “An Evaluation of Pseudo-Random Testing for Detecting Real Defects,” IEEE VLSI Test Symp., pp. 404-409, 2001.

  67. S. Mitra and E.J. McCluskey, “Which Concurrent Error Detection Scheme to Choose?,” IEEE Intl. Test Conf., pp. 985-994, 2000.

  68. S. Mitra and E.J. McCluskey, “Combinational Logic Synthesis for Diversity in Duplex Systems,” IEEE Intl. Test Conf., pp. 179-188, 2000.

  69. S. Mitra and E.J. McCluskey, “WORD VOTER: A New Voter Design for Triple Modular Redundant Systems,” IEEE VLSI Test Symp., pp. 465-470, 2000.

  70. S. Mitra, N. Saxena and E.J. McCluskey, “Fault Escapes in Duplex Systems,” IEEE VLSI Test Symp., pp. 453-458, 2000.

  71. P. Shirvani, S. Mitra, J. Ebergen, and M. Rocken, “DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits,” Intl. Symp. Asynchronous Circuits and Systems, pp. 73-82, 2000.

  72. S. Mitra, N.R. Saxena, and E.J. McCluskey, “A Design Diversity Metric and Reliability Analysis For Redundant Systems,” IEEE Intl. Test Conf., pp. 662-671, 1999.

  73. P. Shirvani, S. Mitra, et al., “Fault-Tolerance Projects at Stanford CRC,” Military Applications Programmable Devices Conf., P23, 1999.

  74. S. Mitra, L.J. Avra and E.J. McCluskey, “An Output Encoding Problem and a Solution Technique,” IEEE/ACM Intl. Conf. Computer-Aided Design, pp. 304-307, 1997.

  75. S. Mitra, L.J. Avra and E.J. McCluskey, “Scan Synthesis for One-hot Signals,” IEEE Intl. Test Conf., pp. 714-722, 1997.

 

Refereed Workshop Publications:

  1. M. Agarwal, B. Paul, M. Zhang and S. Mitra, “Circuit Failure Prediction,” IEEE Intl. Workshop on Silicon Errors in Logic -- System Effects, 2007.

  2. J. Bau, Q. Jacobson, R. Hankins, B. Saha, A. Tabatabai and S. Mitra, “Error Resilient System Architecture for Probabilistic Applications,” IEEE Intl. Workshop on Silicon Errors in Logic -- System Effects, 2007.

  3. M. Agarwal, B. Paul, M. Zhang and S. Mitra, “On-line Failure Prediction and Its Application to Transistor Aging,” IEEE Timing Analysis and Optimization Workshop, 2007.

  4. S. Mitra, M. Zhang, N. Seifert, B. Gill, S. Waqas and K.S. Kim, “Combinational Logic Soft Error Correction,” IEEE System Effects of Logic Soft Errors Workshop, 2006.

  5. S. Venkataraman, S. Mitra and N. Basturkmen, “Diagnosis in the Presence of Test Compression using X-Compact,” IEEE International Workshop on Electronic Design, Test and Applications, 2006 (Invited).

  6. S. Mitra, M. Zhang, N. Seifert, Q. Shi, T.M. Mak and K.S. Kim, “Built-In Soft Error Resilience Structures,” IEEE System Effects of Logic Soft Errors Workshop, 2005.

  7. A. Hirudayaraj, S. Mitra and K.S. Kim, “Xpand + X-Compact: Key Learnings,” IEEE Intl. Test Synthesis Workshop, 2004.

  8. E. Volkerink and S. Mitra, “Response Compaction in the Presence of Any Number of Unknowns,” IEEE Intl. Workshop Infrastructure IP, 2003.

  9. S. Mitra and K.S. Kim, “Test Cost Reduction through Response Compaction,” IEEE Testing Embedded Core-based Systems Workshop, 2002 (Invited).

  10. S. Mitra, C.W. Tseng, J.C.M. Li and E.J. McCluskey, “Pseudo-Random Testing: Theoretical Models vs. Real Data,” IEEE Intl. Test Resource Partitioning Workshop, 2001.

  11. S. Mitra, N.R. Saxena and E.J. McCluskey, “Evaluation and Design of Dependable Systems with Design Diversity,” Evaluating & Architecting System Dependability, pp. 31-35, 2001.

  12. N.S. Oh, S. Mitra and E.J. McCluskey, "EDDDDI: Error Detection by Diverse Data and Duplicated Instructions," High Performance Embedded Computing, 2000.

  13. S. Mitra, N.R. Saxena and E.J. McCluskey, “Non-Self-Testable Faults in Duplex Systems,” IEEE Intl. High-Level Design Validation and Test, pp. 102-109, 1999.

  14. S. Mitra, P.P. Shirvani and E.J. McCluskey, “Fault Location in FPGA Based Reconfigurable Systems,” IEEE International High Level Design Validation and Test, 1998.

  15. S. Mitra and E.J. McCluskey, “An Output Encoding Technique for Delay Fault Testability,” IEEE Intl. Test Synthesis Workshop, 1998.