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Tao of EE183
      

Forbidden pins on the XS40

The following pins on the XS40 board are DEFINITELY NOT okay to use for input/output to/from the FPGA:

P1  GND
P2  VCC
P11 VCC
P12 GND
P13 CLK (internal oscillator 12MHz)
P21 GND
P22 VCC
P31 GND
P32 Parallel port data
P33 VCC
P34 Parallel port data
P35 GLOBAL CLOCK - use it, but only to input the clock signal! (with BUFGE)
P36 uC Reset (Erin thinks this is OK, but Gulli is doubtful)
P43 GND
P52 GND (hook this up to external ground)
P54 VCC
P55 PROGRAM
P61 SRAM Output Enable
P63 GND
P64 VCC
P74 VCC
P76 GND

The pins marked GND can be connected to external ground, (and at least one of them must be). But do NOT connect anything to the VCC pins!!!

On the following pins, opinions differ or they'll work only under certain conditions:

P15 TDI Erin believes this is OK. John says it's hooked up to 4010 pin 71!
P16 TCK John suspects this one of foul play but isn't sure.
P17 TMS John suspects this one of foul play but isn't sure.
P30 Serial EEPROM chip-enable -- but the serial EEPROM isn't present on our boards!
P37 uC Clock -- John uses it. Probably okay if the uC is disabled (uC Reset, pin 36)
P46-49 John says these are OK iff you unplug the parallel cable
P60 bad acc. to Erin, but John is using it
P62 bad acc. to Erin, but John is using it
P65 bad acc. to Erin, but John is using it
P66 bad acc. to Erin, but John is using it
P67 bad acc. to Erin, but John is using it
P71 John says this pin on the 4010 is hooked up to pin 15
    on the board, NOT pin 71, but will work when used accordingly.

Here's what John Coiner had to say on the matter:

Pins 15, 16, 17 - I had bad luck with these. Board would wedge after a few clock cycles if it showed signs of life at all. Tried without parallel cable. Tried both normal pads and the funky alternative pads the xs40 docs say to use. No luck. UPDATE: Later on I realized the same symptoms were happening without using 15,16,17 but with a much lower MTBF... and it was caused by a bad clock to my system... so maybe 15-17 are not so bad. Your mileage may vary.

Pin 30 - None of the boards have serial eeproms on them. So best of luck enabling them accidently. Pin 30 works great for me. I used the special alternative pad the xs40 docs suggest.

36 + 37 - I'm using 37, was doubtful of 36 and am not using it (didn't try). If you really needed them you could pull the uC off. It would surprise me if these two cause problems when used together (would need to see uC datasheet)

60-62, 65-67 - I'm using all but pin 61 as bidirectional I/O pins. Works OK. I left out 61 because it's output enable on the onboard RAM. And you could pull the RAM off if you needed it, or if you're using RAM, you could use the onboard RAM... anyway pins that are not assigned float up to 5V and so the onboard RAM is harmless if this pin is not assigned. I have no reason to believe , it will just tend to cause the onboard RAM to do things intended or otherwise.

71 - The first time I went looking at the datasheet for info on 71, I didn't see it attached to anything, so I figured I could use it. Turns out that XCBUS71 is not hooked up to the 4010XL's pin 71, it's the only XCBUS pin not tied to the corresponding 4010XL pin. 4010XL pin 71 is tied to XCBUS 15. Dollars to donuts, placing a pad at loc 71 in your schematic and wiring it to pin 15 on the xcbus would work, i haven't tried this. Even tho i had a problem with pin 15, that happened even when 15 was wired as an input. 4010 pin 15 is messed up, but xcbus 15 is prolly fine, it looks like it's wired to the parallel cable and 4010 pins 71 and 15 and nothing else (so try sans parallel cable if you try this).

All other pins are, as far as we know, OK to use for general purpose FPGA input/output.