Digital Multiplier Design & Optimization

Advised by: Dr. Binsu J Kailath, PhD

Assosciate Professor,

Dept. of Electronics & Communications,

Indian Institute of Information Technology (IIIT)

Digital multipliers are the building blocks of modern DSP chips, but they are also one of the most power hungry units in any ALU and ultimately determine its speed. As a result, it is always beneficial to develop high performance, low power multipliers.

My senior year undergrad thesis at Indian Institute of Information Technology (IIIT) was on designing highly optimum, digital multipliers through innovative use of arithmetic constructs and number theory. I designed and implemented a new, integrated 128–bit Digital Multiplier based on the Vedic Sutras (a set of algorithms that make calculations faster, claimed to have been derived from ancient Indian scriptures), for which I received the Institute Gold Medal and the Best Project Award.

Various strategies based on a combination of chip design and digital logic algebra were implemented to develop the optimum multiplier in terms of power consumption, delay and area occupied. The proposed design had achieved an optimum time delay, area occupancy and minimum power consumption of 4.971 ns, 75013 sq.nm and 28.73 mW respectively.

You can find my thesis titled “Design of an Optimized Low Power Vedic Multiplier (MAC) Unit for Digital Signal Processing Applications” here