Publications
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"Plasticine: A Reconfigurable Architecture For Parallel Patterns",
ISCA '17: 44th International Symposium on Computer Architecture, Toronto, Canada, 06/2017.
Abstract
Download: paper (1.53 MB)
"TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory",
The 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Xi'an, China, 04/2017.
Download: paper (1.93 MB); slides (1.06 MB)
"Automatic Generation of Efficient Accelerators for Reconfigurable Hardware",
The 43rd International Symposium on Computer Architecture (ISCA), Seoul, South Korea, 06/2016.
Abstract
Download: paper (2.77 MB)
"Generating Configurable Hardware from Parallel Patterns",
Twenty First International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Atlanta, GA, 04/2016.
Abstract
Download: paper (582.67 KB)
"The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplane",
ACM Trans. Comput. Syst., vol. 34, no. 4, New York, NY, USA, ACM, pp. 11:1–11:39, 2016.
Download: 2016.ix_.tocs_.pdf (1.18 MB)
"The IX Operating System: Combining Low Latency, High Throughput, and Efficiency in a Protected Dataplane",
ACM Trans. Comput. Syst., vol. 34, no. 4, New York, NY, USA, ACM, pp. 11:1–11:39, 2016.
"IX: A Protected Dataplane Operating System for High Throughput and Low Latency",
Proceedings of the 11th USENIX Conference on Operating Systems Design and Implementation, Broomfield, CO, USA, USENIX Association, pp. 49–65, 2014.
Download: paper (309.07 KB)
"Towards Energy-proportional Datacenter Memory with Mobile DRAM",
Proceedings of the 39th Annual International Symposium on Computer Architecture, Washington, DC, USA, IEEE Computer Society, pp. 37–48, 2012.
Download: paper (5.08 MB)
"Implementing and Evaluating a Model Checker for Transactional Memory Systems.",
ICECCS: IEEE Computer Society, pp. 117-126, 2010.
Download: paper (286.35 KB)
"Implementing and evaluating nested parallel transactions in software transactional memory.",
SPAA: ACM, pp. 253-262, 2010.
Download: paper (449.46 KB)
"Transactional Memory Coherence and Consistency",
Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, pp. 102–, 6/2004.
"Scalable Vector Processors for Embedded Systems",
IEEE Micro, vol. 23, no. 6, pp. 36–45, 11/2003.
"Overcoming the limitations of conventional vector processors",
Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), San Diego, CA, pp. 399–409, 06/2003.
"Vector vs. Superscalar and VLIW Architectures for Embedded Multimedia Benchmarks",
Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO), Istanbul, Turkey, pp. 283–293, 11/2002.