We can only see a short distance ahead, but we can see plenty there that needs to be done.
Alan Turing
Stergios Stergiou
About me
I am a member of the research staff of Fujitsu Laboratories of America. Between 2001 and 2003 I did my first PhD on ``Optimization Algorithms for Boolean Expressions with Equivalence Gates'' at the National Technical University of Athens. I received my MS from the University of Patras and my CS degree from the National Kapodistrian University of Athens.
Publications
| [1] |
Stergios Stergiou and George Papakonstantinou.
Exact minimization of ESOP expressions with less than eight product terms.
International Journal of Circuits, Systems and Computers,
13(1), 2004. [ .pdf ] |
| [2] |
Stergios Stergiou, Dimitris Voudouris, and George Papakonstantinou.
Multiple-value exclusive-or sum-of-products minimization algorithms.
IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, E87-A(5), 2004. [ .pdf ] |
| [3] |
Dimitris Voudouris, Stergios Stergiou, and George Papakonstantinou.
Minimization of reversible wave cascades.
IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, E88-A(4), 2005. [ .pdf ] |
| [4] |
Davide Bertozzi, Antoine Jalabert, Srini Murali, Rutu Tamhankar, Stergios
Stergiou, Luca Benini, and Giovanni De Micheli.
Noc synthesis flow for customized domain specific multiprocessor
systems-on-chip.
IEEE Transactions on Parallel and Distributed Systems, 16(2),
2005. [ .pdf ] |
| [5] |
R. Tamhankar, S. Murali, Stergios Stergiou, A. Pullini, F. Angiolini,
L. Benini, and Giovanni De Micheli.
Timing error tolerant networks on chip design methodology.
IEEE Transactions on Computer Aided Design, 26(7), 2007. [ .pdf ] |
| [6] |
Stergios Stergiou and Jawahar Jain.
Novel Applications of a Compact Binary Decision Diagrams Library to
Important Industrial Applications.
Fujitsu Scientific and Technical Journal, 2010-1 (vol.46, No.1).
(invited) [ .pdf ] |
| [7] |
Stavros Cosmadakis, Kleoni Ioannidou, and Stergios Stergiou.
View serializable updates of concurrent index structures.
In Proceedings of the 8th International Symposium on Databases
and Programming Languages, pages 247 - 262, 2001. [ .pdf ] |
| [8] |
G. Economakos, Stergios Stergiou, G. Papakonstantinou, and V. Zoukos.
A multi-lingual synthesis and verification environment.
In Proceedings of the Euromicro Symposium on Digital Systems
Design, pages 8 - 15, 2001. [ .pdf ] |
| [9] |
N. Papaspyrou, I. Panagopoulos, Stergios Stergiou, and G. Papakonstantinou.
Developing embedded applications for a component-based operating
system.
In Information Society, 2001. [ .pdf ] |
| [10] |
N. Papaspyrou, Stergios Stergiou, G. Manis, and G. Papakonstantinou.
A meta - interface for programming embedded applications in a tailor
- made operating system.
In International Workshop on Computer Science and Information
Technologies, 2002. |
| [11] |
Stergios Stergiou and G. Papakonstantinou.
An efficient exact esop minimization algorithm.
In International Conference on VLSI, 2002. [ .pdf ] |
| [12] |
Stergios Stergiou, A. Sotiropoulos, A. Alexandridi, and G. Manis.
Rapid context switching on an fpga custom processor with a
configurable number of registers.
In IEEE International Workshop on System-On-Chip for Real-Time
Applications, 2002. [ .pdf ] |
| [13] |
Stergios Stergiou, G. Manis, G. Asimenos, A. Sotiropoulos, and
G. Papakonstantinou.
A novel reconfigurable processor architecture with hardware assisted
os kernel.
In Workshop on Application Specific Processors (MICRO35), 2002. [ .pdf ] |
| [14] |
Stergios Stergiou and G. Papakonstantinou.
Towards a promising general novel exact esop minimization
methodology.
In 6th International Symposium on Representations and
Methodology of Future Computing Technology (RM'03), 2003. [ .pdf ] |
| [15] |
Stergios Stergiou, K. Daskalakis, and G. Papakonstantinou.
A fast and efficient heuristic esop minimization algorithm.
In Proceedings of the 14th ACM Great Lakes symposium on VLSI,
pages 78 - 81, 2004. [ .pdf ] |
| [16] |
Stergios Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, and
Giovanni De Micheli.
xpipes lite: A synthesis oriented design library for networks on
chips.
In Proceedings of the International Conference on Design
Automation and Test in Europe, 2005. [ .pdf ] |
| [17] |
Stergios Stergiou and Jawahar Jain.
Disjunctive transition relation decomposition for efficient
reachability analysis.
In Proceedings of the IEEE International High Level Design
Validation and Test Workshop, 2006. [ .pdf ] |
| [18] |
Stergios Stergiou and Jawahar Jain.
Optimizing Routing Tables on Systems-on-Chip with Content-Addressable Memories
In Proceedings of the IEEE International System-on-Chip Symposium,
2008. [ .pdf ] |
| [19] |
Stergios Stergiou and Jawahar Jain.
Disjunctive Transition Relation Decompositions for Multithreaded Image Computation
In Proceedings of the 14th Asia and South Pacific Design Automation Conference,
2009. [ .pdf ] |
| [20] |
Stergios Stergiou and Jawahar Jain.
Dynamically Resizable Binary Decision Diagrams.
In Proceedings of the 20th Great Lakes VLSI Conference,
2010. [ .pdf ] |
| [21] |
Stergios Stergiou.
Implicit Permutation Enumeration Networks and Binary Decision Diagrams Reordering.
In Proceedings of the 48th Design Automation Conference,
2011. [ .pdf ] (best paper nomination) |