PATENTS:

1. N. Patil and S. Mitra, “Nanotube Circuits,” filed in 2007.

2. J. Tschanz, S. Mitra and V. De, “Error Detection Flip-flop,” filed by Intel Corporation, 2006.

3. J. Tschanz, S. Mitra and V. De, “Degradation Compensation using Body Bias,” filed by Intel Corporation, 2006.

4. S. Mitra, M. Zhang and K.S. Kim, “System and Shadow Bistable Circuits Coupled to Output Joining Circuit,” filed by Intel Corporation, 2005.

5. T.M. Mak, M. Zhang, S. Mitra and P. Shipley, “System Pulse Latch and Shadow Pulse Latch Coupled to Output Joining Circuit,” filed by Intel Corporation, 2005.

6. S. Mitra, K.S. Kim, T.M. Mak, Q. Shi and M. Zhang, “System and Shadow Circuits with Output Joining Circuit,” US Patent 7,278,074.

7. S. Mitra, M. Zhang, V. Zia and T.M. Mak, “System and Scanout Circuits with Error Resilience Circuit,” US Patent 7,278,076.

8. S. Mitra, K.S. Kim and T.M. Mak, “Error Detecting Circuits,” US Patent 7,188,284.

9. S. Mitra and K.S. Kim, “Generalized Response Compactor Designs,” filed by Intel Corporation, 2003.

10. S. Mitra and K.S. Kim, “Response Compactor Designs,” US Patent 7,185,253.

11. S. Mitra and K.S. Kim, “Deterministic Stimulus Generator,” US Patent 7,240,260.

12. S. Mitra and E.J. McCluskey, “Voter Designs for Redundant Systems,” US Patent 6,910,173.