S. O'Driscoll and T.H. Meng,
"Adaptive ADC Design for Neuro-Prosthetic Interfaces,"
Wireless Research Forum,
National Taiwan University,
Taipei, May 25, 2004. (Invited)
Design of serial input buffer and PLL Loop Filter and characterization of jitter tolerance for clock and data recovery PLL for 200MBPS to 1.5 GBPS SERDES physical layer interface using SiGe BiCMOS process.
Design of bandgap voltage regulator to give accurate 2.5V rail from 1.2V supply in 0.13um CMOS process.
Team leader for group of four junior engineers and interns.
