EDUCATION
Stanford University, Stanford, CA [Expected March 2010]
Master of Science in Electrical Engineering
GPA: 3.857/4.0
Coursework: Machine Learning, Artificial Intelligence Research Project, Computer Vision,
Data Visualization,
Computational Advertising, Processor architecture, Object Oriented Systems,
Databases, Networks
Indian Institute of Technology Kharagpur, India [July 2004 to
May 2008]
Bachelor of Technology (Honors) in Computer Science and Engineering
GPA: 9.11/10.0
Coursework: Algorithms, Artificial Intelligence, Operating Systems, Computer Architecture, Advanced Network Technologies,
Principles of Microprocessors, Cryptography and Network Security
SKILLS
Programming skills: C, Java
Web: Javascript, PHP, HTML
Technologies: Virtualization (VMware), Drools Rule Engine, Version Control Systems (SVN), gdb, OpenCV library
Database:
MySQL, XML, XPath, XQuery, Microsoft Access
Development Environments:
Microsoft Visual Studio 2008, Eclipse IDE, Net Beans IDE
Engineering software: Matlab FPGA Development: Altera Quartus II, SOPC Builder, Altera Nios II IDE Hardware Simulations: ModelSim, Quartus II PowerPlay Power Analyzer
WORK EXPERIENCE
Vision-Controlled
Autonomous Indoor Helicopter [Sept
2008 - Present]
- Using computer vision, depth perception and supervised machine learning techniques to
autonomously navigate radio-controller helicopters in restricted indoor
environments
- Developed vision and control framework for autonomous panning along
user-defined trajectories.
Supervisor: Dr. Andrew Ng, AI Lab, Stanford University. Working in
collaboration with Ashutosh Saxena
IIT Kharagpur - Undergraduate Thesis [Jan 2007 - May 2008]
Project Title: "Design of a Low Power Microcontroller for Wireless
Sensor Networks"
- Designed a low-power, event driven microcontroller tailored for use in
wireless sensor network nodes.
- Power simulations suggest one to two orders of magnitude reduction in power
dissipation over existing microcontrollers for sensor network applications
Supervisors: Prof. Ajit Pal, Dept. of Computer Science and Engineering,
IIT Kharagpur
Microsoft Research, Redmond, WA - Summer Internship [May - July
2007]
Project Title: "Energy Optimization for Future Storage Technology"
- Designed, implemented and evaluated a novel software-compression based memory
management framework to minimize energy consumption of Flash Memory in sensor
nodes and sensor network gateways.
Supervisors: Dr. Suman Nath & Dr. Aman Kansal, Networked Embedded
Computing Group, MSR
Nanyang Technological University, Singapore - Summer Internship
[May - July 2006]
Project Title: "Efficient Implementation of Custom Instructions on
Reconfigurable Instruction Set Processors"
- Proposed hybrid macro models to characterize benefits and tradeoffs offered by
the different custom instruction architectures on Nios II softprocessors
- First in-depth research study of its kind on the problem of identification of
best architectural implementation of custom instructions on reconfigurable
platforms.
Supervisors: Dr. Thambipillai Srikanthan, Center for High Performance
Embedded Systems and Siew Kei, NTU
TEACHING EXPERIENCE
Stanford University - Course Assistant [Sept - Dec 2008]
- Course Assistant for CS143 - Compilers, Fall 2008
Professor: Dr. Alexander Aiken, Computer Science Department, Stanford
University
MAJOR
PROJECTS
Analyzing Author-Coauthor Collaboration Networks in DBLP Bibliography
[Sept 2008 - Jan 2009]
- Developed a web scraper for extracting author information and affiliations
from the DBLP Computer Science Bibliography and online resources
- Implemented framework to structure information into relational databases and
run queries to extract author-coauthor relationships. Network analysis on
relevant data was done using Pajek tool
Supervisor: Dr. Rebecca Slayton, Program in Science, Technology and
Society, Stanford University
A Nios II Softprocessor based Self-Adaptive QRS Detection System
[Jan – August 2007 ]
- A novel adaptive algorithm-bank based solution to QRS complex detection for
accurate identification of heartbeat anomalies under varying environmental
conditions.
- Implemented a Nios II based system optimized for performance, area and energy
efficiency.
Supervisor: Dr. Ajit Pal, Department of Computer Science and
Engineering, IIT Kharagpur
Project awarded 2nd prize at the Altera 2007 Nios II Embedded
Processor Design Contest
Complexity of External Memory Sorting and Related Algorithms on Flash Memory
[Jan – April 2007]
- A qualitative analysis of the difference in fundamental I/O
complexity of a class of flash memory based external-memory algorithms and their
conventional hard-disk counterparts.
Supervisor: Prof. Pabitra Mitra, Dept. of Computer Science &
Engineering, IIT Kharagpur
- Electrocardiogram (ECG) Acquisition, Processing & Monitoring System
for Telemedicine Application [Jan – April 2006]
- Developed an FPGA-based system (Altera Nios-II processor) and
frontend interface for data acquisition from an analog ECG machine with data
storage, display and transmission functionalities.
Supervisor: Dr. Ajit Pal, Department of Computer Science and
Engineering, IIT Kharagpur
Project sponsored by Ministry of Human Resource and Development
(MHRD), New Delhi, India
TERM
PROJECTS & PRESENTATIONS
AuctionBase: Online Auction Website with PHP and MySQL [Sept – Dec
2008]
- Developed a completely functional online auction website with search,
browse and bidding capabilities. Front end interface was designed using PHP and
backend design involved parsing XML into relational tables and implementing an
embedded SQL query interface.
Inverse Transliterator & Spell Checker for Hindi [Sept – Nov 2007]
- Implemented an inverse transliterator for converting Romanized Hindi
to Devanagari script in C. A spell-checker was also added for accurate results,
given the phonetic soundness of Hindi.
Dynamic Power Estimation for Sequential Circuits [August – Nov
2007]
- Developed software for real-time evaluation of average, peak and
per-clock power of digital sequential circuits based on logic simulation.
Reliable Communication over an Unreliable Link [Feb - April 2007]
- Designed and implemented a software framework to ensure reliable,
in-order, exactly-once communication over an unreliable link employing UDP
sockets
Softprocessor based Digit Recognition System using Neural Networks [Feb
– April 2006]
- Nios II processor based digit recognition system using single hidden
layer neural network. System acquires input through photo-sensor array and
identifies digit based on trained data.