RESEARCH WORK
"Vision Controlled
Autonomous Indoor Helicopter", Stanford University [Sept 2008 -
Present]
Indoor navigation of aerial vehicles poses several challenges in sustaining
hover flights. The key challenges are the high presence of obstacles in
constrained environments, frugal payload budget and the need for real-time
control response. We successfully apply computer vision and machine learning
techniques for autonomously panning RC helicopters in fixed indoor settings. Our
framework uses images of the environment to ‘learn’ its surrounding and perform
attitude estimation on live-streaming data from an onboard wireless camera using
the learned model. Our controller is capable of hovering the helicopter in
place, sustaining orientation with respect to reference points and following
panning trajectories.
Supervisor: Dr. Andrew Ng, AI Lab, Stanford University. Working in collaboration with Ashutosh Saxena
2:00 AM on a random night, AI Lab, Stanford University, November 2008
Bachelors Thesis Project
"Design of Low-Power Microcontroller for Wireless Sensor Networks”,
IIT Kharagpur [January 2007 - May 2008]
Abstract: My thesis work involved the design of a low-power event
driven microcontroller with a powerful interrupt structure for real-time event
handling, low power sleep modes and fast context switching. The project utilized
an application-driven approach to the architectural design and implementation of
a microcontroller for wireless sensor network nodes that recognizes the
event-driven nature of many sensor-network workloads. We performed an extensive
study of WSN workloads and applications to form the basis of the architecture.
The MCU is tailored for low-power operation in Wireless Sensor Network (WSN)
nodes and applications. Our results suggest one to two orders of magnitude
reduction in power dissipation over existing commodity based systems for an
important class of sensor network applications.
Supervisor: Prof. Ajit Pal, Dept. of Computer Science & Engineering, IIT
Kharagpur
Summer
Internships
"Energy Optimization for Future Storage Technology",
Networked Embedded Computing, Microsoft Research, Redmond [May - July 2007]
Abstract: The popularity of high-density flash memory as the choice of
data storage media has increased steadily for a wide spectrum of technologies,
including PDAs, mobile phones and digital cameras. More recently, computer
manufacturers have started launching new lines of portable computers that have
done away with magnetic disk drives altogether, replacing them with tens of
gigabytes of NAND flash memory. It is thus not inconceivable to consider running
a full database system on the flash-only computing platforms or running an
embedded database system on the lightweight computing devices. Flash memories
are used particularly in energy aware environments, where battery life is more
important that storage capacity. Along these lines, we present the design of a
new framework called the Software Compression Layer (SCL) for flash memory
devices. The framework is designed to exploit data compression as a primary
means of minimizing energy utilization in flash memories in order to achieve
optimal performance and low power consumption. The overall design decisions are
modeled taking into account the unique characteristics of the flash memory,
resulting in an elegant software based solution to dramatically decrease energy
consumption, without hardware or application level changes. The system was
evaluated on sensor netowrk workloads and FlashDB (Dynamic self Tuning Database
for NAND Flash) and suggests significant power savings (>25%).
Supervisors: Suman Nath & Aman Kansal, Researchers, Networked Embedded
Computing, Microsoft Research, Redmond, WA
(View Performance Appraisal Certificate)
"Efficient Implementation of Custom Instructions on Reconfigurable
Instruction Set Processors", Centre for High Performance Embedded
Systems, Nanyang Technological University, Singapore [May - July 2006]
Abstract: This project involved a study of an efficient methodology for
implementing computation intensive custom instructions on Altera Nios II, a
commercially available extensible processor. Existing Instruction Set Extension
(ISE) techniques do not consider the problem of determining the best possible
implementation of custom instructions on a given platform. Our solution to the
above problem is a study and derivation of hybrid macro models for different
customization parameters. We explore the technique of instruction set clustering
based on operation subset sharing, and the advantages it offers when implemented
using the extended architecture, and compare/contrast it with other
architectures. This provides a definite characterization of the benefits and
tradeoffs of the available implementation methodologies to aid the designer
determine the most suited architecture. Such a characterization is facilitated
by careful analysis of the microarchitectural details and their variation with
certain parameters to satisfy user provided metric constraints. We validated the
proposed methodology by characterizing and modeling the delay, maximum clocking
frequency and the area overhead of a state-of-art extensible processor (Altera's
Nios II) using automatically and manually generated extensible instructions. We
used the macro model for choosing the best architecture for implementation and
analyzed the benefits obtained for several benchmark applications with custom
instructions.
Supervisors: Dr. Thambipillai Srikanthan and Mr. Lam Diew Kei, CHiPES,
Nanayang Technological University, Singapore
(View Performance Appraisal Certificate)
Major Projects
"A Nios II Softprocessor based Self-Adaptive QRS Detection System"
[Jan – August 2007 ]
Abstract: We propose a novel adaptive algorithm-bank based solution to
the problem of QRS complex detection under varying environmental/patient
conditions. Our method uses periodic sampling of the input ECG signal, and a
dynamic decision is taken to find the most appropriate algorithm for QRS
detection. A careful analysis of the conditions under which a complementary set
of algorithms perform optimally has been performed and a protocol for the
dynamic decision making process has been devised. The sampling imposes
significantly less computational overhead and the adaptive switching solves the
algorithm-suitability problem. Our resulting design is optimized for performance
and energy and hence can be incorporated in a wide spectrum of medical settings,
including power-conscious hand-held devices necessitating accurate heart beat
monitoring, like the Holter systems.
Supervisor: Dr. Ajit Pal, Department of Computer Science and
Engineering, IIT Kharagpur
Project awarded 2nd Prize at the Altera 2007 Nios II Embedded Processor Design
Contest (Asia Pacific Region)
"Complexity of External Memory Sorting and Related Algorithms on Flash
Memory" [Jan – April 2007]
Abstract: We consider the essential problem of examining the
fundamental limits in terms of the number of I/Os for external sorting and
related problems in the flash memory computing environments, which differs
significantly in characteristics from its hard-disk counterparts. Such a
detailed analysis, among its other uses, can be used by database system
designers for query processing and optimization. As we note, the performance of
certain algorithms on flash memory are comparable to their hard disk
counterparts, however certain other algorithms perform poorly in flash devices
due to the inherent I/O bottleneck and flash-specific characteristics. Hence, a
broad overview of the complexity of specific classes of algorithms is essential
in determining its suitability for flash memory. To the best of our knowledge,
ours is the first work of its kind that analyzes the complexity of a class of
algorithms for operation on flash devices.
Supervisor: Prof. Pabitra Mitra, Dept. of Computer Science &
Engineering, IIT Kharagpur
"Electrocardiogram (ECG) Acquisition, Processing and Monitoring System
for Telemedicine Application" [Jan – April 2006 ]
Abstract: Electrocardiogram (ECG) is the most commonly used biomedical
signal for diagnostic purpose. It can be used to diagnose heart disease,
identify cardiac arrhythmias, and evaluate effect of drugs. In this project, we
have presented the design and implementation an FPGA based system using
techniques to delineate the ECG signal. We are designing and implementing an
Altera Nios-II softprocessor based system for clinical use. It can be used to
acquire ECG signal from the patient and display it on a graphical LCD. The
signal is analyzed to delineate PQ, QRS and ST complexes and derive parameters
like heart beat rate and PR, PQ and QT intervals. The system adheres to the
standards and protocols specified by HL7. Applications to revolutionize health
care systems in non-urban parts of the country.
Supervisor: Dr. Ajit Pal, Department of Computer Science and
Engineering, IIT Kharagpur
Project sponsored by Ministry of Human Resource and Development (MHRD), New
Delhi, India
A random afteroon, Hardware Lab, IIT Kharagpur, Late 2005. My lab partner and I, after a tiring one month in the hardware lab, on completion of the design and implementation of the 4-bit CPU. My first stint at digital circuity and hardware - the feel of watching what we'd toiled over for over a month work flawlessly was exhilarating !