Richard M. Yoo

Transactional Memory Systems

Adaptive Transaction Scheduling for Transactional Memory Systems

Transactional memory systems can excel traditional lock-based systems only when the executing workloads contain sufficient parallelism. We observed that when the workload lacks the inherent parallelism, blindly launching excessive transactions can adversely result in performance degradation. This is due to the increased loss in ineffective transactions. By adaptively adjusting the number of concurrently executing transactions according to the parallelism feedback from the workload, we can significantly increase transaction effectiveness.

A transaction scheduler based on this study not only guarantees that hardware transactional memory systems perform better than locks, but also showed significant performance improvement for both the hardware and software transactional memory systems.

Related publications:

Richard M. Yoo and Hsien-Hsin S. Lee.
"Adaptive Transaction Scheduling for Transactional Memory Systems."
in Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), Special Track on Hardware and Software Techniques to Improve the Programmability of Multicore Machines, pp. 169-178, Munich, Germany, June 2008. [ppt]

Helper Transactions: Enabling Thread-Level Speculation via A Transactional Memory System

Thread-Level Speculation (TLS) has been researched as a parallelization technique to automatically extract possibly non-conflicting multiple threads of execution from a single-threaded program. Transactional memory systems, on the other hand, have recently been appreciated as a parallelism-enabling technique on multi-core processors due to its radically simple programming semantics.

In this research we discuss how transactional memory systems can be extended to enable thread-level speculation techniques. Especially, among the many TLS techniques, we propose a detailed design to effectively exploit out-of-order procedure fall-through speculation. In this design, speculatively executed transactions gracefully degenerate to helper threads in the worst case.

Related publications:

Richard M. Yoo and Hsien-Hsin S. Lee.
"Helper Transactions: Enabling Thread-Level Speculation via A Transactional Memory System."
in the 2008 Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures (PESPMA), held in conjunction with the 35th ACM/IEEE International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008. [ppt]

Workload Characterization and Performance Analysis

Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis

Benchmark suite scores are typically calculated by averaging the performance of each individual workload. Therefore, the scores are inherently affected by the distribution of workloads, in particular, from workload redundancy. Redundancy in the workloads of a benchmark suite renders the benchmark scores biased, making the score of a suite susceptible to malicious tweaks. SPECjvm2007, for example, suffers from high workload redundancy due to the merger with SciMark 2.

We propose a set of benchmark suite score calculation methods, the hierarchical means that incorporate cluster analysis to amortize the negative effect of workload redundancy. These methods not only improve the accuracy and robustness of the score, but also improve the objectiveness over the weight-based approach.

This research is a joint effort with SSG / MRTD at Intel Corporation.

Related publications:

Richard M. Yoo, Hsien-Hsin S. Lee, Han Lee, and Kingsum Chow.
"Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis."
in Proceedings of the 2007 IEEE International Symposium on Workload Characterization (IISWC), pp. 204-213, Boston, MA, September 2007. [ppt]

Constructing a Non-Linear Model with Neural Networks for Workload Characterization

Due to their stacked execution environment, J2EE applications tend to exhibit high non-linearity; workload performance does not improve or degrade in a linear fashion as we linearly adjust configurable parameters. In this research we developed an accurate non-linear workload behavior model with artificial neural networks to help tune the application.

In our case study on a workload resembling SPECjAppServer2004 the model showed 95% accuracy in predicting the workload performance.

This research is a joint effort with SSG / MRTD at Intel Corporation.

Related publications:

Richard M. Yoo, Han Lee, Kingsum Chow, and Hsien-Hsin S. Lee.
"Constructing a Non-Linear Model with Neural Networks for Workload Characterization."
in Proceedings of the 2006 IEEE International Symposium on Workload Characterization (IISWC), pp. 150-159, San Jose, CA, October 2006. [ppt]