Professor of Electrical Engineering
H.-S. Philip Wong is the Willard R. and Inez Kerr Bell
Professor in the School of Engineering. He received the B.Sc. (Hons.) in 1982 from the University
of Hong Kong, the M.S. in 1983 from the State University of New York at Stony Brook,
and the Ph.D. in 1988 from Lehigh
University, all in electrical engineering. He joined the IBM T. J. Watson Research Center,
While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.
Professor Wong’s research aims at transforming discoveries in science into useful technologies. His work contributed to the advancements in nanoscale science and technology, semiconductor technology, solid-state devices, and electronic imaging. He explores the use of nano-materials, nanofabrication techniques, and novel device concepts for nanoelectronics systems. Novel devices often enable new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven. Currently, his research covers a broad range of topics including carbon electronics, biosensors, self-assembly, exploratory logic devices, nanoelectromechanical relays, device modeling, and non-volatile memory devices such as phase change memory and metal oxide resistance change memory.
He is a Fellow of the IEEE and served on the IEEE Electron Devices Society (EDS) as elected AdCom member from 2001 – 2006. He served on the IEDM committee from 1998 to 2007 and was the Technical Program Chair in 2006 and General Chair in 2007. He served on the ISSCC program committee from 1998 – 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. Currently, he serves on the Executive Committee of the Symposia of VLSI Technology and Circuits. He was the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 – 2006. He is a Distinguished Lecturer of the IEEE Electron Devices Society (since 1999) and Solid-State Circuit Society (2005 – 2007).
His academic appointments include the Chair of Excellence of the French Nanosciences Foundation, Guest Professor of Peking University, Honorary Professor of the Institute of Microelectronics of the Chinese Academy of Sciences, and the Honorary Doctorate degree from the Institut Polytechnique de Grenoble, France.
RESEARCH GROUP: Nanoelectronics and Nanotechnology (http://nano.stanford.edu)
Keywords: Nanotechnology, nanoelectronics, semiconductor technology, solid-state devices, Si CMOS, solid-state imaging.
School of Engineering Annual Report (2006-2007) – Click on Profiles
Ask the Expert – What is Nanotechnology? – Click here
Education video on nanotechnology:
Logic devices beyond the silicon CMOS device scaling roadmap. Project scope covers new device concepts, device physics, circuit design, modeling, and device fabrication using novel nanoelectronic materials such as carbon nanotube and graphene as well as novel concepts such as nanoelectromechanical (NEM) relays.
We work on circuit-level performance modeling and optimization for end-of-the-roadmap CMOS devices. As devices scale to small dimensions, parasitic capacitances and parasitic resistances play an increasingly important role in circuit/system level performance. We have developed accurate parasitic capacitance and parasitic resistance models to enable circuit/device optimization and to explore new device design options. Compact models for emerging devices such as III-V FETs, carbon nanotube transistor have been developed and continually being refined to enable performance benchmarking and technology assessment at the device and circuit level.
We continue to develop and enhance our carbon nanotube transistor compact device model for circuit simulation. System-level optimization is enabled by the development of non-iterative compact models of carbon nanotube transistors. We are working on robust circuit design and fabrication for carbon nanotube and graphene electronics including active devices (carbon nanotubes) and interconnects (graphene). We develop synthesis techniques to achieve high-density, aligned growth of carbon nanotubes as well as low temperature carbon nanotube growth for electronics applications. Both digital logic and high-frequency analog applications are explored.
[Aligned carbon nanotube growth (Albert Lin, Nishant Patil)]
Nanoelectromechanical (NEM) relay represents a departure from the conventional transistors and memories and offers unique advantages such as zero off-state leakage and energy-reversible operation for low standby power and low dynamic power. We work on experimental fabrication of NEM relay and circuits as well as the development of modeling tools for device design and circuit design.
[Nanoelectromechanical (NEM) relay (Soogine Chong, Roozbeh Parsa)]
[Paper Clip Nanoelectromechanical (NEM) relay (Dr. Daesung Lee)]
Memory and storage devices beyond the technology roadmap. The projects scope covers new device concepts, device physics, modeling, and device fabrication. At present, we work in three areas: (1) memory cell selection device, (2) phase change memory, and (3) metal oxide memory (RRAM).
We study the device physics of phase change memory and metal oxide RRAM by fabricating novel device structures that enable detailed electrical characterization of their properties. We perform physics-based modeling to elucidate the physics of switching and construct compact models to explore the use of these memory devices in various applications.
[48 nm x 48 nm cross-point memory (Byoungil Lee)]
[Cross-point phase change memory using carbon nanotube electrode (Jiale Liang)]
[Cross-point metal oxide RRAM using carbon nanotube electrode (Yi Wu)]
· Electronic synapse (NSF, and NRI): We are developing nanoscale electronic devices and circuits to emulate the functions of synapses of the brain. The goal is to use nanoscale electronic devices to help study learning behavior in biology. Currently, we are using phase change memory and metal oxide RRAM to perform gray-scale analog programming of the resistance values. These electronic emulations of the synapse are then connected in a neural network to demonstrate learning behavior.
[nanoelectronic synapse (Duygu Kuzum, Rakesh Jeyasingh)]
· CHIC (Chip-in-Cell) – Autonomous bio-sensor: In-situ detection of chemical changes in human body at the cellular level can bring enormous benefits in diagnosis and in therapeutic monitoring. We are developing techniques to place micron-sized sensor chip inside each cell. It might revolutionize biochemical imaging by introducing the concept of replacing “passive” radiotracers with “active” IC chips. This may open up an array of new biomedical applications from novel medical diagnostic and therapeutic tools that operate at single cell level to a novel class of autonomously operating intrabody nanobiosensors. We are also developing wireless bio-sensors for autonomous, continuous-time, in vivo monitoring.
Use of diblock copolymers for the fabrication of nanoelectronic devices. The focus is on device fabrication and process integration. We had successfully fabricated functional MOSFET and CMOS circuits using diblock copolymer as a patterning technique for features at the sub-20 nm scale. We are now developing directed self-assembly (DSA) technology using small guiding templates with sizes that are comparable to the desired pitch to improve the DSA performance and to provide flexible controls on pitch, shape, and ordering of the self-assembly. These canonical templates, which are akin to the letters of the alphabet, are the most basic features essential to compose a device layout of contact holes. Each template only generate one robust pattern consisting one or a few holes with certain size, shape and ordering. A canonical template database will be set up to cover all the essential patterns for device design. By applying the design rules of DSA, a device can be disassembled to a set of patterns that can be generated by the corresponding canonical templates. On the other hand, designers can also design devices with modified or new layouts to best fit the DSA design rules for optimal patterning. This is a project that crossed the boundaries of materials science, device design, image processing, and computer science.
[Directed Self-Assembly (He Yi)]
[Self-assembled Stanford logo (Li-Wen Chang)]
[Self-assembled Smiley Faces (Li-Wen Chang)]
EE 21N Freshman Seminar (new class, Autumn, 2006, next offerings: Winter 2011, Autumn 2011, Winter 2012, Winter 2013) – “What is Nanotechnology?”
Textbooks: "Engines of Creation: The Coming Era of Nanotechnology" by Eric Drexler (Anchor Books 1986), and "Prey" by Michael Crichton (Harper Collins 2002).
EE 320 (evolved from EE 218, new in 2008/09, Spring 2009, next offerings: Spring 2011, Spring 2013, in alternate years) “Nanoelectronics” (There is no required textbook for this course) – Prerequisite EE222, EE216 and knowledge of solid state physics, Recommended: EE 223, 228, or 316.
EE 316 (Winter) “Advanced VLSI Devices”
(Winter) (with Prof. Krishna Saraswat and Prof.
EE 309 (new class, Spring, 2006, next offering: Spring 2014, offered in alternate years) “Semiconductor Memory Devices and Technology” (There is no required textbook for this course) – Prerequisite: EE 216. Preferred: EE 316, EE 313, EE 311
EE 392B (Spring, 2005, not offered in the near future) “Introduction to Image Sensors and Digital Cameras” (with Prof. Abbas El Gamal)
EE 310 Seminar slides:
October 5, 2004. Download here. (rather old, kept here for historical reasons, as a time capsule)
H.-S. Philip Wong
Department of Electrical Engineering and Center for Integrated Systems,
Paul G. Allen 312X
Email: hspwong AT stanford DOT edu
Administrative Assistant: Fely Barrera
Selected Recent and Upcoming Conference Publications:
1. H.-Y. Chen, H. Tian, B. Gao, S. Yu, J. Liang, J. Kang, Y. Zhang, T.-L. Ren, H.-S. P. Wong, “Electrode/Oxide Interface Engineering by Inserting Single-Layer Graphene: Application for HfOx–Based Resistive Random Access Memory,” IEEE International Electron Devices Meeting (IEDM), paper 20.5, December 9 – 12, San Francisco, 2012.
2. H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. Kang, and H.-S. P. Wong, “HfOx Based Vertical RRAM for Cost-Effective 3D Cross-Point Architecture without Cell Selector,” IEEE International Electron Devices Meeting (IEDM), paper 20.7, December 9 – 12, San Francisco, 2012.
3. S. Yu, X. Guan, and H.-S. P. Wong, “Understanding Metal Oxide RRAM Current Overshoot and Reliability Using Kinetic Monte Carlo Simulation,” IEEE International Electron Devices Meeting (IEDM), December 9 – 12, San Francisco, 2012.
4. S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, and H.-S. P. Wong, “A Neuromorphic Visual System Using RRAM Synaptic Devices with Sub-pJ Energy and Tolerance to Variability: Experimental Characterization and Large-Scale Model,” IEEE International Electron Devices Meeting (IEDM), paper 10.4, December 9 – 12, San Francisco, 2012.
5. K. B. Parizi, A.J. Yeh, A. S. Y. Poon, H.-S. P. Wong, “Exceeding Nernst Limit (59mV/pH): CMOS-Based pH Sensor not Requiring a Reference Electrode for Autonomous Applications,” IEEE International Electron Devices Meeting (IEDM), paper 24.8, December 9 – 12, San Francisco, 2012.
6. X. Chen, D. H. Seo, S. Seo, H. Chung, H.-S. P. Wong, “Graphene Interconnect Lifetime under High Current Stress,” Symp. VLSI Technology, paper T14-2, pp. 121 – 122, June 12 – 15, 2012.
7. H. Yi, X.-Y. Bao, C. Bencher, H. Dai, Y. Chen, H.-S. P. Wong, “Design Space for One-hole Pattern using Block Copolymer Directed Self-Assembly,” 56th International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), paper 10B-05, Waikoloa, Hawaii, May 29 – June 1, 2012.
8. J. Liang, S. Yeh, S. S. Wong, H.-S. P. Wong, “Scaling Challenges for the Cross-point Resistive Memory Array to Sub-10nm Node – An Interconnect Perspective,” International Memory Workshop (IMW), Milan, Italy, pp. 61 – 64, May 20 – 23, 2012.
9. Y. Wu, S. Yu, H.-S. P. Wong, “AlOx-based Resistive Switching Device with Gradual Resistance Modulation for Neuromorphic Device Application,” International Memory Workshop (IMW), Milan, Italy, pp. 111 – 114, May 20 – 23, 2012.
10. H. Yi, X.-Y. Bao, J. Zhang, R. Tiberio, J. Conway, L.-W. Chang, S. Mitra, H.-S. P. Wong, “Contact Hole Patterning for Random Logic Circuits using Block Copolymer Directed Self-Assembly,” SPIE Symposium on Advanced Lithography, Conferences on Alternative Lithographic Technologies IV, paper 8323-31, San Jose, CA, February 12-16, 2012. Proc. SPIE 8323, 83230W (2012); http://dx.doi.org/10.1117/12.912804
11. S. Chong, B. Lee, K.B. Parizi, J. Province, S. Mitra, R.T. Howe, H.-S. P. Wong, “Integration of Nanoelectromechanical (NEM) Relays with Silicon CMOS with Functional CMOS-NEM Circuit,” IEEE International Electron Devices Meeting (IEDM), paper 30.5, pp. 701 – 704, December 5 – 7, Washington, D.C., 2011.
12. D. Kuzum, R.G.D. Jeyasingh, H.-S. P. Wong, “Energy Efficient Programming of Nanoelectronic Synaptic Devices for Large-Scale Implementation of Associative and Temporal Sequence Learning,” IEEE International Electron Devices Meeting (IEDM), paper 30.3, pp. 693 – 696, December 5 – 7, Washington, D.C., 2011.
13. H. Wei, H.-Y. Chen, L. Liyanagi, H.-S. P. Wong, “Air-Stable Technique for Fabricating n-Type Carbon Nanotube FETs,” IEEE International Electron Devices Meeting (IEDM), paper 23.2, pp. 505 – 508, December 5 – 7, Washington, D.C., 2011.
14. S. Yu, X. Guan, H.-S. P. Wong, “On the Stochastic Nature of Resistive Switching in Metal Oxide RRAM: Physical Modeling, Monte Carlo Simulation, and Experimental Characterization,” IEEE International Electron Devices Meeting (IEDM), paper 17.3, pp. 413 – 416, December 5 – 7, Washington, D.C., 2011.
15. S. Yu, R.G.D. Jeyasingh, Y. Wu, H.-S. P. Wong, “Understanding the Conduction and Switching Mechanism of Metal Oxide RRAM through Low Frequency Noise and AC Conductance Measurement and Analysis,” IEEE International Electron Devices Meeting (IEDM), paper 12.1, pp. 275 – 278, December 5 – 7, Washington, D.C., 2011.
16. X.-Y. Bao, H. Yi, C. Bencher, L.-W. Chang, H. Dai, Y. Chen, H.-S. P. Wong, “ SRAM, NAND, DRAM Contact Hole Patterning using Block Copolymer Directed Self-assembly Guided by Small Topographical Templates,” IEEE International Electron Devices Meeting (IEDM), paper 7.7, pp. 167 – 170, December 5 – 7, Washington, D.C., 2011.
17. J. Zhang, N. Patil, H.-S. P. Wong, S. Mitra, “Overcoming Carbon Nanotube Variations through Co-optimized Technology and Circuit Design,” IEEE International Electron Devices Meeting (IEDM), paper 4.6, pp. 87 – 90, December 5 – 7, Washington, D.C., 2011.
Recent Invited Journal Articles:
1. M. Caldwell, R.G.D. Jeyasingh, H.-S. P. Wong, D. Milliron, “Nanoscale Phase Change Memory Materials,” invited feature article Nanoscale, vol. 4, pp. 4382 – 4392 (2012). DOI: 10.1039/C2NR30541K
2. J. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S. P. Wong, S. Mitra, “Robust Digital VLSI using Carbon Nanotubes,” invited keynote paper, IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 31, No. 4, pp. 453 – 471, 2012. DOI: 10.1109/TCAD.2012.2187527
3. H.-S. P. Wong, H.-Y. Lee, S. Yu, Y.-S. Chen, Y. Wu, P.-S. Chen, B. Lee, F.T. Chen, M.-J. Tsai, “Metal Oxide RRAM,” invited paper, Proceedings of the IEEE, vol. 100, No. 6, pp. 1951 – 1970, June, 2012.
4. H.-S. P. Wong, S. Raoux, S. Kim, J. Liang, J.P. Reifenberg, B. Rajendran, M. Asheghi, K.E. Goodson, “Phase Change Memory,” invited paper, Proceedings of the IEEE, Vol. 98, No. 12, pp. 2201 – 2227, December 2010.
Selected Recent Journal Articles:
1. D. Kuzum, R.G.D. Jeyasingh. S. Yu, H.-S. P. Wong, “Low-Energy Robust Neuromorphic Computation Using Synaptic Devices,” IEEE Trans. Electron Device, vol. 59, issue 12, pp. 3849 – 3894 (2012). DOI: 10.1109/TED.2012.2217146
2. X. Chen, D. H. Seo, S. Seo, H. Chung, H.-S. P. Wong, “Graphene Interconnect Lifetime: A Reliability Analysis,” IEEE Electron Device Letters, vol. 33, issue 11, pp. 1604 – 1606, 2012. DOI: 10.1109/LED.2012.2211564
3. J. Parker, C. Beasley, A. Lin, H.-Y. Chen, H.-S. P. Wong, “Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes.” Carbon 50:5093-8, 2012.
4. X. Guan, S. Yu, H.-S. P. Wong, “A SPICE Compact Model of Metal Oxide Resistive Switching Memory with Variations,” IEEE Electron Device Letters, vol. 33, No.10, pp. 1405 – 1407, October 2012. DOI: 10.1109/LED.2012.2210856
5. H. Yi, X.-Y. Bao, J. Zhang, C. Bencher, L.-W. Chang, X. Chen, R. Tiberio, J. Conway, H. Dai, Y. Chen, S. Mitra, and H.-S. P. Wong, “Flexible Control of Block Copolymer Directed Self-Assembly using Small Topographical Templates: Potential Lithography Solution for Integrated Circuits Contact Hole Patterning,” Advanced Materials, vol. 24, issue 23, pp. 3107 – 3114, 2012. DOI: 10.1002/adma.201200265
6. J. Hu and H.-S. P. Wong, “Effect of Annealing Ambient and Temperature on the Electrical Characteristics of ALD Al2O3/ In0.53Ga0.47As MOSCAPS and MOSFETs,” J. Appl. Phys., accepted for publication, 2012.
7. C. Ahn, B. Lee, R.G.D. Jeyasingh, M. Asheghi, G.A.M. Hurkx, K.E. Goodson, H.-S. P. Wong, “Effect of Resistance Drift on the Activation Energy for Crystallization in Phase Change Memory,” Jpn. J. Appl. Phys., 51, 02BD06, 2012. DOI: 10.1143/JJAP.51.02BD06.
8. Y. Wu, S. Yu, B. Lee, and H.-S. P. Wong, “Low-Power TiN/Al2O3/Pt Resistive Switching Device with Sub-20μA Switching Current and Gradual SET and RESET,” J. Applied Physics, 110, pp. 094104-1 – 094104-5 (2011). http://dx.doi.org/10.1063/1.3657938
9. D. Kuzum, R.G.D. Jeyasingh, B. Lee, H.-S. P. Wong, “Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing,” Nano Letters, 12 (5), pp 2179–2186, 2012. Web publication date: June 14, 2011. DOI: 10.1021/nl201040y.
10. L.S. Liyanage, H. Lee, N. Patil, S. Park, S. Mitra, Z. Bao, H.-S.P. Wong, “Wafer Scale Fabrication and Characterization of Thin Film Transistors with Polythiophene Sorted Semiconducting Carbon Nanotube Networks,” ACS Nano, 6 (1), pp 451–458, 2012.
11. S. Yu, X. Guan, H.-S. P. Wong, “On the Switching Parameter Variation of Metal Oxide RRAM – Part II: Model Corroboration and Device Design Strategy,” IEEE Trans. Electron Devices, vol. 59, no. 5, pp. 1183 – 1188, 2012. DOI: 10.1109/TED.2012.2184544
12. X. Guan, S. Yu, H.-S. P. Wong, “On the Switching Parameter Variation of Metal Oxide RRAM – Part I: Physical Modeling and Simulation Methodology,” IEEE Trans. Electron Devices, vol. 59, no. 5, pp. 1172 – 1182, 2012. DOI: 10.1109/TED.2012.2184545
13. J. Liang, R.G.D. Jeyasingh, H.-Y. Chen, H.-S. P. Wong, “An Ultra-low Reset Current Cross-point Phase Change Memory with Carbon Nanotube Electrodes,” IEEE Trans. Electron Devices, vol. 59, no. 5, pp. 1155 – 1163, 2012. DOI: 10.1109/TED.2012.2184542
14. S. Yu, R. Jeyasingh, Y. Wu, H.-S. P. Wong, “Characterization of Low Frequency Noise in the Resistive Switching of Transition Metal Oxide HfO2,” Physical Review B, 85, 045324-1 – 045324-4 (2012).
15. Y. Chai, A. Hazeghi, K. Takei, H.-Y. Chen, S. Yu, P.C.H. Chan, A. Javey, H.-S. P. Wong, “Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer,” IEEE Trans. Electron Devices, vol. 59, No. 1, pp. 12 – 19, 2012.
16. S. Chong, B. Lee, S. Mitra, R.T. Howe, H.-S. P. Wong, “Integration of Nanoelectromechanical Relays with Silicon nMOS,” IEEE Trans. Electron Devices, vol. 59, No. 1, pp. 255 – 258, January 2012.
17. S. Yu, Y. Y. Chen, X. Guan, H.-S. P. Wong, J. A. Kittl, “A Monte Carlo study of the low resistance state retention of HfOx based resistive switching memory,” Appl. Phys. Lett. 100, pp. 043507-1 – 043507-4 (2012); doi: 10.1063/1.3679610
Selected Publications Prior to Joining Stanford:
1. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The Road to the End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.
2. H.-S. P. Wong, “Beyond the Conventional Transistor,” Solid State Electronics, vol. 49, pp. 755 – 762 (2005).
3. J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, H.-S. P. Wong, „Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation with Ni,” IEEE Trans. Electron Devices, vol. 51, No. 12, pp. 2115 – 2120 (2004).
4. D.V. Singh, K.A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill, H.-S. P. Wong, “Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors,” IEEE Trans. Nanotechnology, vol. 3, no. 3, pp. 383 – 387 (2004).
5. H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 135 – 137 (2004).
6. J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S. P. Wong, “Extension and Source/Drain Design for High-Performance FinFET Devices,” IEEE Transactions on Electron Devices, vol. 50, No. 4, pp. 952 – 958, April, 2003.
7. H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, “Electrical Characterization of Germanium p-Channel MOSFETs,” IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003.
8. X. Wang, H.-S. P. Wong, P. Oldiges and R.J. Miller, “Electrostatic Analysis of Carbon Nanotube Arrays,” 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, September 3 – 5, 2003.
9. H.-S. P. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, Ph. Avouris, “Carbon Nanotube Field Effect Transistors – Fabrication, Device Physics, and Circuit Implications”, IEEE International Solid State Circuits Conference (ISSCC), p. 370 – 371, 2003.
10. H.-S. P. Wong, “Beyond the Conventional Transistor”, invited paper, IBM J. Research & Development, March/May, pp. 133-168, 2002.
11. J. Kedzierski, E. Nowak, Thomas Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 247 – 250, 2002
12. Z. Ren, S. Hedge, B. Doris, P. Oldiges, T. Kanarsky, O. Dokumaci, M. Ieong, E. C. Jones, H.-S. P. Wong, “An Experimental Study on Electrostatics and Transport Issues of Ultra-Thin Body SOI pMOSFETs”, IEEE Electron Device Letters, Vol. 23, No. 10, pp. 609-611, October, 2002.
13. L.J. Huang, J.O.Chu, S. Goma, C.P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes, J. L. Speidell, R. M. Anderson, H.-S. P. Wong, “Electron and Hole Mobility Enhancement in Strained Silicon-On-Insulator by Wafer Bonding,” IEEE Trans. Electron Devices, Vol. 49, pp. 1566 – 1571, September, 2002.
14. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, F.-F. Jamin, L. Shi , W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, M. Gribelyuk , E.C. Jones, R.J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling With Ultra-Thin Silicon Channel MOSFET’s (XFET)”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 267 – 270, 2002.
15. K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B.H. Lee, A. Mocuta, J. Welser, S.L. Cohen, M. Ieong, and H.-S. P. Wong, “Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics”, Symp. VLSI Technology, pp. 12-13, June, 2002.
16. R. Martel, H.-S. P. Wong, K. Chan, and Ph. Avouris, “Carbon Nanotube Field Effect Transistors for Logic Applications”, IEEE International Electron Devices Meeting (IEDM), Washington, D.C., pp. 159-162, 2001.
17. D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, invited paper, IEEE Proceedings, Special Issue on The Limits of Semiconductor Technology, pp. 259-288, March, 2001.
18. H.-S. P. Wong, D.J. Frank, P.M. Solomon, H.-J. Wann, J. Welser, “Nanoscale CMOS'', IEEE Proceedings, invited paper, Special Issue on Quantum Devices and Applications, pp. 537-570, April, 1999.
Recent and Upcoming Invited Presentations:
1. Y. Wu, S. Yu, H.-Y. Chen, J. Liang, Z. Jiang, H.-S. P. Wong, "Resistive Switching Random Access Memory (RRAM) – Materials, Device, Scaling, and Array Design," invited paper, 60th International Symposium of the American Vacuum Society (AVS), Long Beach, CA, October 27 – November 1, 2013.
2. H. Yi, H.-S. P. Wong, " Alphabet-Based Template Design Rules - A Key Enabler for a Manufacturable DSA Technology," invited paper, 60th International Symposium of the American Vacuum Society (AVS), Long Beach, CA, October 27 – November 1, 2013.
3. S. Yu, X. Guan, Y. Wu, H.-S. P. Wong, “Characterization and Modeling of the Conduction and Switching Mechanism of HfOx based RRAM,” invited paper, MRS Fall 2013 Symposium on “Emergent Electron Transport Properties at Complex Oxide Interfaces”, Boston, MA, 2013
4. H.-Y. Chen, S. Yu, Y. Wu, H.-S. P. Wong, “3D Vertical RRAM Architecture and Electrode/Oxide Interface Engineering for Next Generation Mass Storage,” invited paper, International Conference on Solid State Devices and Materials (SSDM), Fukuoka, Japan, September 24-27, 2013.
5. J. Parker, X. Chen, L. Liyanage, A. Tang, H.-S. P. Wong, “Carbon 1D/2D Nanoelectronics: Advances in Synthesis and Integration,” invited paper, 223rd ECS Meeting, Symposium E2: “Graphene, Ge/III-V, and Emerging Materials for Post CMOS Applications 5,” Toronto, Ontario, Canada, May 12-16, 2013.
6. H.-S. P. Wong, “Emerging Memory Devices,” keynote talk, China Semiconductor Technology International Conference (CSTIC), Symposium VI: “Materials and Process Integration for Device and Interconnection,” Shanghai, China, March 17 – 18, 2013.
7. H. Yi, H.-S. P. Wong, “Directed Self-Assembly for Random Logic Circuits – An Opportunity for Design Tool Development,” keynote talk, China Semiconductor Technology International Conference (CSTIC), Symposium I: Device Engineering and Technology, Shanghai, China, March 17 – 18, 2013.
8. H.-S. P. Wong, “Semiconductor Technologies for N+m Nodes, where m≥4,” invited paper, IEEE Texas Workshop on Integrated System Exploration (TexasWISE), Winedale, TX, March 8, 2013.
9. H.-S. P. Wong, “Electronic Synaptic Devices,” invited paper, 9th Kavli Futures Symposium: The Intersection of Nanoscience and Neuroscience at UC Berkeley, January 10 – 11, 2013.
10. D. Kuzum, R. J. D. Jeyasingh, S. B. Eryilmaz, S. Yu, and H.-S. P. Wong, “Programming Phase Change Synaptic Devices for Neuromorphic Computation,” Symposium EE on "Phase-Change Materials for Memory, Reconfigurable Electronics and Cognitive Applications" invited talk, Spring Meeting of the Materials Research Society (MRS), San Francisco, April 1 – 5, 2013.
February 7, 2013