H.-S. Philip Wong

wong_VG1U5164_crop

 

Professor of Electrical Engineering

 

Education:

B.Sc. Hons. (1982) University of Hong Kong, M.S. (1983) State University of New York, Stony Brook, and Ph.D. (1988) Lehigh University. 

 

Biography:

Prof. Wong joined Stanford in September, 2004 after 16 years at IBM Research, T.J. Watson Research Center, Yorktown Heights, New York. While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.

 

His research interests are in nanoscale science and technology, semiconductor technology, solid state devices, and electronic imaging. He is interested in exploring new materials, novel fabrication techniques, and novel device concepts for future nanoelectronic systems. Novel devices often enable new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven. His present research covers a broad range of topics including carbon nanotubes, semiconductor nanowires, self-assembly, exploratory logic devices, nanoelectromechanical devices, novel memory devices, and biosensors.

 

He is a Fellow of the IEEE and served on the IEEE Electron Devices Society (EDS) as elected AdCom member from 2001 – 2006. He served on the IEDM committee from 1998 to 2007 and was the Technical Program Chair in 2006 and General Chair in 2007. He served on the ISSCC program committee from 1998 – 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. Currently, he serves on the Executive Committee of the Symposia of VLSI Technology and Circuits. He was the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 – 2006. He is a Distinguished Lecturer of the IEEE Electron Devices Society (since 1999) and Solid-State Circuit Society (2005 – 2007). He has taught several short courses at the IEDM, ISSCC, Symp. VLSI Technology, SOI conference, and SPIE conferences. He is a member of the Emerging Research Devices Working Group of the International Technology Roadmap for Semiconductors (ITRS).

 

 

RESEARCH GROUP: Nanoelectronics and Nanotechnology (http://nano.stanford.edu)

Keywords: Nanotechnology, nanoelectronics, solid-state devices, Si CMOS, solid-state imaging.

School of Engineering Annual Report (2006-2007) – Click on Profiles

Education video on nanotechnology:

Carbon nanotube technology (funded by the National Science Foundation)

 

CURRENT PROJECTS:

 

Nanoscale CMOS Device Physics and Device Design (FCRP MSD, FCRP C2S2, NSF, Stanford INMP, Industry funding)

Currently, we are working on two topics: (1) III-V compound semiconductor as a channel material for high-performance CMOS, and (2) circuit-level performance modeling and optimization for end-of-the-roadmap CMOS devices. Transport-enhanced channel materials will improve FET device performance. We are developing contact technologies for III-V FETs. The experimental work is coupled with modeling to enable optimization of the contact design. We also develop compact modeling tools for III-V FET circuit design and performance benchmarking. As devices scale to small dimensions, parasitic capacitances and parasitic resistances play an increasingly important role in circuit/system level performance. We develop accurate parasitic capacitance and parasitic resistance models to enable circuit/device optimization and to explore new device design options.

 

Nanoelectronic Devices (FCRP C2S2, FCRP IFC, FCRP FENA, NSF, DARPA)

Logic devices beyond the silicon CMOS device scaling roadmap. Project scope covers new device concepts, device physics, circuit design, modeling, and device fabrication using novel nanoelectronic materials such as carbon nanotube and semiconductor nanowires as well as novel concepts such as nanoelectromechanical (NEM) relays.

 

We continue to develop and enhance our carbon nanotube transistor compact device model for circuit simulation. System-level optimization is enabled by the development of non-iterative compact models of carbon nanotube transistors. We are working on robust circuit design and fabrication for carbon nanotube electronics including active devices and interconnects (wiring). We develop synthesis techniques to achieve high-density, aligned growth of carbon nanotubes as well as low temperature carbon nanotube growth for electronics applications. Both digital logic and high-frequency analog applications are explored. Recent work has included explorations into graphene for active device and wiring applications.

[Aligned carbon nanotube growth (Albert Lin, Nishant Patil]

 

Nanoelectromechanical (NEM) relay represents a departure from the conventional transistors and memories and offers unique advantages such as zero off-state leakage and energy-reversible operation for low standby power and low dynamic power. We work on experimental fabrication of NEM relay and circuits as well as the development of modeling tools for device design and circuit design.

 [Nanoelectromechanical (NEM) relay (Soogine Chong, Roozbeh Parsa)]

 

Novel Memory and Storage Devices (CIS Seed Funding, SRC, Stanford NMTRI, Industry funding, LBNL Molecular Foundry)

Memory and storage devices beyond the technology roadmap. The projects scope covers new device concepts, device physics, modeling, and device fabrication. At present, we work in three areas: (1) memory cell selection device, (2) phase change memory, and (3) metal oxide memory. The main topics include (a) novel pn-junction diode and other novel memory cell selection device, (b) device physics and scaling trend of phase change memory and metal oxide memory (e.g. NiO), (c) synthesis and properties of phase change nanoparticles, (d) new phase change memory cell structure design that can provide high reliability, low power consumption, and possibly multi-bit operation, and (e) modeling of memory device physics. Memory cell designs are tested with simulation tools using multi-physics simulation tools that incorporate electrical conduction, heat conduction and phase change. We are developing methodologies to measure the thermal properties of phase change materials, including nanometer-sized phase change materials for better device modeling and device design. We are also exploring new materials for phase change memory and metal oxide memory.

[48 nm x 48 nm cross-point memory (Byoungil Lee)]

 

Nano-bio

·         SyNAPSE (DARPA, IBM): We are developing nanoscale electronic devices and circuits to emulate the functions of synapses and neurons at the complexity of the brain of a rat and a cat.

 [nanoelectronic synapse (Byoungil Lee)]

 

·         CHIC (Chip-in-Cell): In-situ detection of chemical changes in human body at the cellular level can bring enormous benefits in diagnosis and in therapeutic monitoring.  We are developing techniques to place micron-sized sensor chip inside each cell. It might revolutionize biochemical imaging by introducing the concept of replacing “passive” radiotracers with “active” IC chips.  This may open up an array of new biomedical applications from novel medical diagnostic and therapeutic tools that operate at single cell level to a novel class of autonomously operating intrabody nanobiosensors.

 

Self-Assembly for Nanoelectronics (SRC, NSF, NRI)

Use of diblock copolymers for the fabrication of nanoelectronic devices. The focus is on device fabrication and process integration. Currently, we are focusing on fabrication of a functional MOSFET and CMOS circuits using diblock copolymer as a patterning technique for features at the sub-20 nm scale. A long-term (5 year) goal of this project is to fabricate a functional device array (e.g. diodes, FETs, SRAM cells) using self-assembly.

[Self-assembled Stanford logo (Li-Wen Chang)]

 

Solar Cells (GCEP, LBNL Molecular Foundry)

We are developing solar cells based on semiconductor (Si, Ge, III-V) nanowires.

 

Classes:

EE 21N Freshman Seminar (new class, Autumn, 2006, next offerings: Autumn 2007, Autumn 2008) – “What is Nanotechnology?”

Textbooks: "Engines of Creation: The Coming Era of Nanotechnology" by Eric Drexler (Anchor Books 1986), and "Prey" by Michael Crichton (Harper Collins 2002).

EE 320 (evolved from EE 218, new in 2008/09, Spring 2009, next offerings: Spring 2009) “Nanoelectronics” (There is no required textbook for this course)

             (slides for 1st lecture of EE 218 back in Autumn 2005)

EE 316 (Winter) “Advanced VLSI Devices”

EE 310 (Winter) (with Prof. Krishna Saraswat and Prof. Yoshio Nishi) “EE Seminar”

EE 309 (new class, Spring, 2006, next offering: Autumn, 2007, Autumn 2009) “Semiconductor Memory Devices and Technology” (There is no required textbook for this course) – Prerequisite: EE 216. Preferred: EE 316, EE 313, EE 311

EE 392B (Spring, 2005, not offered in the near future) “Introduction to Image Sensors and Digital Cameras” (with Prof. Abbas El Gamal)

 

EE 310 Seminar slides:

October 5, 2004. Download here. (rather old, kept here for historical reasons)

 

Contacts: 

 

H.-S. Philip Wong

Center for Integrated Systems, Paul G. Allen 312X

Stanford University, Stanford, CA 94305-4075

Email: hspwong AT stanford.edu

Phone: +1-650-725-0982

 

Administrative Assistant: Fely Barerra

Email: fely.barerra AT stanford.edu

Phone: +1-650-723-1349

 

Selected Recent and Upcoming Conference Publications:

 

1.       B.J. Bae, S. Kim, Y. Zhang, Y.K. Kim, I.G. Baek, S.O. Park, I.S. Yeo, S. Choi, J.T. Moon, H.-S. P. Wong, and K. Kim, “1D Thickness Scaling Study of Phase Change Material (Ge2Sb2Te5) using a Pseudo 3-Terminal Device,” IEEE International Electron Devices Meeting (IEDM), paper 5.2, December 6 – 9, Baltimore, 2009.

2.       D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun. P. A. Pianetta, H.-S. P. Wong, K. C. Saraswat, “Experimental Demonstration of High Mobility Ge NMOS,” IEEE International Electron Devices Meeting (IEDM), paper 19.1, December 6 – 9, Baltimore, 2009.

3.       N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson. H.-S. P. Wong, S. Mitra, “VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs,” IEEE International Electron Devices Meeting (IEDM), paper 23.4, December 6 – 9, Baltimore, 2009.

4.       H. Wei, N. Patil, A. Lin, H.-S. P. Wong, S. Mitra, “Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects,” IEEE International Electron Devices Meeting (IEDM), paper 23.5, December 6 – 9, Baltimore, 2009.

5.       X. Chen, K.-J. Lee, D. Akinwande, G. Close, S. Yasuda, B. Paul, S. Fujita, J. Kong, H.-S. P. Wong, “High-Speed Graphene Interconnects Monolithically Integrated with CMOS Ring Oscillators Operating at 1.3GHz,” IEEE International Electron Devices Meeting (IEDM), paper 23.6, December 6 – 9, Baltimore, 2009.

6.       L.-W. Chang, T.L. Lee, C. H. Wann, C.Y. Chang, H.-S. P. Wong, “Top-Gated MOSFETs with Diblock Copolymer Self-Assembled 20 nm Contact Holes,” IEEE International Electron Devices Meeting (IEDM), paper 36.3, December 6 – 9, Baltimore, 2009.

7.       L. Wei, D. J. Frank, L. Chang, H.-S. P. Wong, “A Non-iterative Compact Model for Carbon Nanotube FETs Incorporating Source Exhaustion Effects,” IEEE International Electron Devices Meeting (IEDM), paper 37.7, December 6 – 9, Baltimore, 2009.

8.       S. Chong, K. Akarvardar, R. Parsa, J.-B. Yoon, R.T. Howe, S. Mitra, H.-S. P. Wong, “Nanoelectromechanical (NEM) Relays Integrated with CMOS SRAM for Improved Stability and Low Leakage,” International Conference on Computer-Aided-Design (ICCAD), accepted for presentation, San Jose, November 2 – 5, 2009.

9.       L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, H.-S. P. Wong, “Exploration of Device Design Space to Meet Circuit Speed Targeting 22nm and Beyond,” 2009 International Conference on Solid State Devices and Materials (SSDM 2009), Sendai, Japan, September 23 – 26, 2009.

 

Selected Recent Publications:

 

1.       S. Raoux, H.-Y. Cheng, M. A. Caldewll, H.-S. P. Wong, “Crystallization Times of Ge-Te Phase Change Materials as a Function of Composition,” Applied Physics Letters, vol. 95, 07190-1 – 07190-3 (2009). DOI: 10.1063/1.3212732

2.       N. Patil, A. Lin, E. Myers, K. Ryu, A. Badmaev, C. Zhou, H.-S. P. Wong, S. Mitra, “Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes,” IEEE Trans. Nanotechnology, vol. 8, no. 5, pp. 498 – 504, July, 2009.

3.       D. Akinwande, N. Patil, A. Lin, Y. Nishi, H.-S. P. Wong, “Surface Science of Catalyst Dynamics for Aligned Carbon Nanotube Synthesis on a Full-Scale Quartz Wafer,” J. Phys. Chem., vol. 113, no. 19, pp. 8002 – 8008 (2009).

4.       K. Akarvardar, H.-S. P. Wong, “Ultra-Low Voltage Crossbar Nonvolatile Memory Based on Energy-Reversible NEM Switches,” IEEE Electron Device Letters, vol. 30, No. 6, pp. 626 – 628, June, 2009.

5.       S. Oh, H.-S. P. Wong, “Effect of Parasitic Resistance and Capacitance on Performance of InGaAs HEMT Digital Logic Circuits,” IEEE Trans. Electron Devices, vol. 56, No. 5, pp. 1161 – 1164, May, 2009.

6.       L. Wei, J. Deng, L.-W. Chang, K. Kim, C.T. Chuang, H.-S. P. Wong, “Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap,” IEEE Transactions on Electron Devices, Vol. 56, No.  2, pp. 312 – 320, February, 2009.

7.       A. Lin, N. Patil, K. Ryu, A. Badmaev, L.G. De Arco, C. Zhou, S. Mitra, and H.-S. P. Wong, “Threshold Voltage and On-Off Ratio Tuning for Multiple-tube Carbon Nanotube FETs,” IEEE Trans. Nanotechnology, vol. 8, No. 1, pp. 4 – 9, 2009.

8.       N. Patil, J. Deng, S. Mitra, H.-S. P. Wong, “Circuit-Level Performance Benchmarking and  Scalability Analysis of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, vol. 8, No. 1, pp. 37 - 45, 2009.

9.       G. F. Close, S. Yasuda, B. Paul, S. Fujita, H.-S. P. Wong, “Measurement of Subnanosecond Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit,” IEEE Trans. Electron Devices, vol. 56, No. 1, pp. 43 – 49, January, 2009.

10.    K. Fife, A. El Gamal, H.-S. P. Wong, “A Multi-Aperture Image Sensor with 0.7µm Pixels in 0.11µm CMOS Technology,” IEEE J. Solid State Circuits, vol. 43, No. 12, pp. 2990 – 3005, December, 2008.

11.    D. Akinwande, J. Liang, S. Chong, Y. Nishi, H.-S. P. Wong, “Analytical Ballistic Theory of Carbon Nanotube Transistors: Experimental Validation, Device Physics, Parameter Extraction, and Performance Projection,” Journal of Applied Physics, vol. 104, pp. 124514-1 – 124514-7, December, 2008. DOI: 10.1063/1.3050345

12.    G.F. Close, S. Yasuda, B. Paul, S. Fujita, H.-S. P. Wong, “1-GHz Integrated Circuit With Carbon Nanotube Interconnects and Silicon Transistors,” Nano Letters, Vol. 8, No. 2, pp. 706 – 709, February 13, 2008.

13.    K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauan, G. C. Wan, A. M. Ionescu, R.T. Howe, and H.S.-P. Wong, “Analytical Modeling of the Suspended-Gate FET and Design Insights for Low Power Logic,” IEEE Trans. Electron Devices, vol. 55, No. 1, pp. 48 – 59, January, 2008.

14.    S. Kim, Y. Zhang, J. McVittie, H. Jagannathan, Y. Nishi, H.-S. P. Wong, “Integrating Phase Change Memory Cell with Ge Nanowire Diode for Cross-Point Memory – Experimental Demonstration and Analysis,” IEEE Trans. Electron Devices, vol. 55, No. 9, pp. 2307 – 2313, September, 2008.

15.    J. Deng, H.-S. P. Wong, “A Compact SPICE Model for Carbon Nanotube Field Effect Transistors Including Non-Idealities and Its Application — Part II: Full Device Model and Circuits Performance Benchmarking” IEEE Trans. Electron Devices, vol. 54, No. 12, pp. 3195 – 3205, December, 2007.

 

Selected Publications Prior to Joining Stanford:

 

1.       T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The Road to the End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.

2.       H.-S. P. Wong, “Beyond the Conventional Transistor,” Solid State Electronics, vol. 49, pp. 755 – 762 (2005).

3.       J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, H.-S. P. Wong, „Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation with Ni,” IEEE Trans. Electron Devices, vol. 51, No. 12, pp. 2115 – 2120 (2004).

4.       D.V. Singh, K.A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill, H.-S. P. Wong, “Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors,” IEEE Trans. Nanotechnology, vol. 3, no. 3, pp. 383 – 387 (2004).

5.       H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 135 – 137 (2004).

6.       J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S. P. Wong, “Extension and Source/Drain Design for High-Performance FinFET Devices,” IEEE Transactions on Electron Devices, vol. 50, No. 4, pp. 952 – 958, April, 2003.

7.       H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, “Electrical Characterization of Germanium p-Channel MOSFETs,” IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003.

8.       X. Wang, H.-S. P. Wong, P. Oldiges and R.J. Miller, “Electrostatic Analysis of Carbon Nanotube Arrays,” 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, September 3 – 5, 2003.

9.       H.-S. P. Wong, J. Appenzeller, V. Derycke, R. Martel, S. Wind, Ph. Avouris, “Carbon Nanotube Field Effect Transistors – Fabrication, Device Physics, and Circuit Implications”, IEEE International Solid State Circuits Conference (ISSCC), p. 370 – 371, 2003.

10.    H.-S. P. Wong, “Beyond the Conventional Transistor”, invited paper, IBM J. Research & Development, March/May, pp. 133-168, 2002.

11.    J. Kedzierski, E. Nowak, Thomas Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 247 – 250, 2002

12.    Z. Ren, S. Hedge, B. Doris, P. Oldiges, T. Kanarsky, O. Dokumaci, M. Ieong, E. C. Jones, H.-S. P. Wong, “An Experimental Study on Electrostatics and Transport Issues of Ultra-Thin Body SOI pMOSFETs”, IEEE Electron Device Letters, Vol. 23, No. 10, pp. 609-611, October, 2002.

13.    L.J. Huang, J.O.Chu, S. Goma, C.P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes,  J. L. Speidell, R. M. Anderson, H.-S. P. Wong, “Electron and Hole Mobility Enhancement in Strained Silicon-On-Insulator by Wafer Bonding,” IEEE Trans. Electron Devices, Vol. 49, pp. 1566 – 1571, September, 2002.

14.    B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, F.-F. Jamin, L. Shi , W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, M. Gribelyuk , E.C. Jones, R.J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling With Ultra-Thin Silicon Channel MOSFET’s (XFET)”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 267 – 270, 2002.

15.    K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B.H. Lee, A. Mocuta, J. Welser, S.L. Cohen, M. Ieong, and H.-S. P. Wong, “Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics”, Symp. VLSI Technology, pp. 12-13, June, 2002.

16.    R. Martel, H.-S. P. Wong, K. Chan, and Ph. Avouris, “Carbon Nanotube Field Effect Transistors for Logic Applications”, IEEE International Electron Devices Meeting (IEDM), Washington, D.C., pp. 159-162, 2001.

17.    D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, invited paper, IEEE Proceedings, Special Issue on The Limits of Semiconductor Technology, pp. 259-288, March, 2001.

18.    H.-S. P. Wong, D.J. Frank, P.M. Solomon, H.-J. Wann, J. Welser, “Nanoscale CMOS'', IEEE Proceedings, invited paper, Special Issue on Quantum Devices and Applications, pp. 537-570, April, 1999.

 

Recent and Upcoming Presentations:

 

1.       H.-S. P. Wong, L. Wei, S. Oh, A. Lin, J. Deng, S. Chong, K. Akarvardar, “Technology Projection Using Simple Compact Models,” invited plenary paper, International Conference on Simulation of Semiconductor Devices and Processes, SISPAD 2009, pp. 1 – 8, San Diego, CA, September 9 – 11, 2009.

2.       N. Patil, A. Lin, J. Zhang, H.-S. P. Wong, S. Mitra, “Digital VLSI Logic Technology using Carbon Nanotube FETs: Frequently Asked Questions,” Proc. Design Automation Conference (DAC), San Francisco, CA, pp. 304 – 309,  July 29, 2009.

3.       K. Akarvardar, H.-S. P. Wong, “Nanoelectromechanical Logic and Memory Devices,” invited paper, 215th Meeting of the Electrochemical Society (ECS), paper # 692, Symposium E1 - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 5: New Materials, Processes, and Equipment, San Francisco, CA, May 24 - May 29, 2009.

4.       B. Lee, H.-S. P. Wong, “Fabrication and Characterization of Nanoscale Non-volatile Memory Using Nickel Oxide Thin Film,” invited paper, Materials Research Society (MRS) Spring Meeting, Symposium V “Functional Metal-Oxide Nanostructures”, paper V2.1, San Francisco, CA, April 13 – 17, 2009

5.       H.-S. P. Wong, “Beyond Si CMOS Scaling – What’s Next?” ISTC/CSTIC 2009 (International Semiconductor Technology Conference) and CSTIC (China Semiconductor Technology International Conference), invited keynote speech, Symposium VIII “Emerging Semiconductor Technologies”, March 19 – 20, Shanghai, China.

6.       Y. Zhang, S. Kim, B. Lee, M. Caldwell, H.-S. P. Wong, “Fabrication and Characterization of Emerging Nanoscale Memory,” invited paper, International Disk Drive Equipment and Materials Association (IDEMA) Technical Symposium, “What's in Store for Storage, The Future of Non-Volatile Technologies,” San Jose, CA, paper 5.3, December 11, 2008.

7.       S. Kim, Y. Zhang, B. Lee, M. Caldwell, H.-S. P. Wong, “Fabrication and Characterization of Emerging Nanoscale Memory,” invited paper, International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 24 – 27, 2009.

 

Last modified:

September 18, 2009