I am currently a third-year Ph.D. student with the Department of Electrical Engineering at Stanford University. My studies are supported by a Prof. Michael J. Flynn Stanford Graduate Fellowship.
My current research interests include computer architecture in general, and networks-on-chip in particular. I am currently working on router microarchitecture in Prof. William J. Dally's Concurrent VLSI Architecture group.
In June 2005, I finished my studies at the Rheinisch-Westfälische Technische Hochschule Aachen, Germany, with a "Dipl.-Ing." degree in Electrical Engineering and Information Technology. I completed my degree with honors and received a Springorum Denkmünze award.
For mydiploma thesis, I investigated the use of Deterministic and Stochastic Petri Nets (DSPNs) for performance modeling in the context of Network-on-Chip architectures. The thesis was written under the supervision of Prof. Tobias G. Noll.
With the support of a Fulbright scholarship, I spent the 2002/2003 academic year at the University of Washington's department of electrical engineering as a visiting graduate student.
During my studies in Germany, I was also supported by a Prof. Dr. Koepchen scholarship from 2003 to 2005; furthermore, I received student scholarships for Apple Computer, Inc.'s yearly World-Wide Developers Conference in 2003, 2004 and 2005, and I was a member of the Infineon Student MemberChip Program during the final year of my studies.
From August 2005 to September 2007, I worked as a hardware development engineer for IBM Deutschland Entwicklung GmbH in Böblingen, Germany.
My job responsibilities included the design and implementation of what in IBM-speak is called "pervasive logic" (roughly, anything on the chip that is not part of mainline functionality, such as the performance monitor, timer facilities, power management, etc.) for high-performance server microprocessors. Two patent applications submitted in the course of my work are currently pending.
Prior to finishing my studies, I worked as an intern for Siemens Corporate Research, Inc. in Redmond, WA, during the summer of 2004; the internship focused on embedded software development for a USB DECT adapter.
(Also available in BibTeX format.)
Daniel U Becker and William J Dally. Allocator implementations for network-on-chip routers. In SC '09: Proceedings of the 2009 ACM/IEEE Conference on High Performance Computing, Networking, Storage and Analysis, 2009. [ bib | DOI | .pdf | Abstract ]
Holger Blume, Thorsten von Sydow, Daniel U Becker, and Tobias G Noll. Application of deterministic and stochastic petri-nets for performance modeling of noc architectures. Journal of Systems Architecture, 53(8):466-476, 2007. [ bib | DOI | .pdf | Abstract ]
Holger Blume, Thorsten von Sydow, Daniel U Becker, and Tobias G Noll. Modeling noc architectures by means of deterministic and stochastic petri nets. In SAMOS '05: Proceedings of the 5th International Workshop on Systems, Architecture, Modeling and Simulations, pages 374-383, 2005. [ bib | DOI | .pdf | Abstract ]
Allocator Implementations for Network-on-Chip Routers. Presented at SC '09, Portland, OR, Nov. 14-20, 2009. [ .pptx ]
Networks on Chip: Router Microarchitecture & Network Topologies. Presented at ST Microelectronics, Crolles, France, Oct. 13, 2009. [ .pptx ]
My current resumé can be downloaded here.
You can reach me at dub@doemail.org.