1. Debugging an IP Router

Supervisor: Dr. Subhashish Mitra, Stanford University.
Platform & Tools: Linux, Verilog, Virsim, IRSIM, Modelsim.

Details: In this project we were provided with an implementation of a 3 port IP router in Verilog HDL. The IP router accepts incoming packets, does a checksum test and routes the packets to appropriate destination port. We were responsible for developing a verilog testbench to check the functionality correctness of the IP router. The test patterns (packets) were generated using a C++ program. The bugs in the implementation were identified and analyzed using Virsim/Modelsim. Finally, a functionally correct version of the IP router was submitted.

2. Implementing the LPM module of an IP Router in System Verilog

Supervisor: Dr. Subhashish Mitra, Stanford University.
Platform & Tools: Linux, Verilog, Virsim, IRSIM, Modelsim.

Details: In this project we designed the Longest Prefix Match (LPM) module of an IP router. The LPM module creates and dynamically updates a Look Up Table (LUT) based on which the routing is done. Moreover, it performs a Linear Search on the LUT entries to match the incoming IP address of a packet with the masked Subnet IP of various destination ports in the LUT. Amongst all matches it finally locates the longest prefix match to determine the Next Hop IP of an ingress packet.

3. Using the knowledge of System Architecture to improve the performance of an N-body Physical Simulation Kernel

Supervisor: Dr. Christos Kozyrakis, Stanford University.
Platform & Tools: Linux, C.

Details: In this project, we were provided with a naive implementation of the motion of N particles in a 2-Dimensional space acted upon by mutual gravitational and repulsive forces. The runtime of many applications (including this one) are bottlenecked by the memory stall cycle time. We developed algorithms and efficient data structures that improved the performance of the naive implementation by increased temporal and spatial locality that in turns decreases L1/L2 miss rates and memory stall cycle time. We used various techniques like prefetching, loop fission/fusion/unrolling, compiler and trigonometric optimization in this project.

4. Development of a Parallel Application for a small-scale cluster.

Supervisor: Dr. Christos Kozyrakis, Stanford University.
Platform & Tools: Linux, C.

Details: The aim of this project was to expose parallelism in an application and to hide communication latency and other overheads associated with parallel execution. We carried out data decomposition and load balancing of the N-body simulation application and developed a parallel program using Message Passing Interface(MPI) library functions. An almost linear speed up was observed due to parallelization.

5. SRAM Design

Supervisor: Dr. Mark Horowitz, Stanford University.
Platform & Tools: Linux, HSpice, Sue.

Details: In the first part of the project, we designed and implemented the basic components of the memory system in HSpice: the decoder, the sense amp, and the memory array. In addition, we computed the latency of our design and analyzed power consumption of the memory system. Finally, we performed a simple read operation to confirm that our design works.In the second part of the project, we used some of the state-of-the-art circuit design techniques taught in class to create a high performance low power SRAM. In the decoder we used appropriately sized skewed static gates, pulsed wordline and self-resetting gates to save power. In the amp section, we used clocked sense amplifier, decoder and bitline replica to accurately model the delay of sense amp enable signal. In the memory core we used wordline partitioning scheme. We also used low-swing signals and low-VT transistors to turn on the bitline precharge. The bitlines were also precharged to Vdd/2 to save memory core power which is a bottleneck in power consumption in SRAM circuits. Finally, we used the HSPICE modeling methods of the previous assignment to validate the improvement in our design.

6. Embedded Systems Firmware Project

Supervisor: Max Klein, Stanford University
Development Environment: AVR Studio

In this project, I was responsible for developing firmware for detection of Dallas One Wire Temperature Sensor on our Dev Board, read the ambient temperature as indicated by the sensor and display it on an LCD screen. The sensor uses a One Wire Protocol. Further details on the protocol may be obtained from pdf. Error detection capability that is available with the device (ie CRC checks on the temperature) was also implemented in firmware. In case corrupt data was read, the data was rejected and read again. After temperature display for a few seconds FreeRTOS was started up for remaining tasks like Global Positioning System (GPS), Accelerometer/Digital Compass (I2C) and Secure Digital Card (SPI).