Mr GAEL CLOSE

Stanford University, Center for Integrated Systems , Stanford (CA), USA
Stanford Nanoelectronics Group (Laboratory of Prof. H-.S. Philip Wong)

Research assistant, 2004-present

I designed, fabricated, and tested the first prototype integrated circuit co-integrating silicon CMOS transistors and carbon nanotube interconnects operating above 1GHz. This prototype serves as a platform for benchmarking carbon nanotubes interconnects. Research project included:

·      Circuit design, layout and verification of the prototype CMOS integrated circuit in Cadence

·      Extensive cleanroom work to develop a process for assembling carbon nanotube interconnects

·      Electrical measurements, including RF measurements and design of a PCB for the test bench

Stanford University, Stanford (CA), USA

Ph.D., Electrical Engineering, expected June 2008
Dissertation title: On-chip demonstration of carbon nanotube interconnects
Advisor: Prof. H.-S. Philip Wong

Master of Science, Electrical Engineering, December 2004
Grade Point Average: 3.96/4.00

Coursework: Analog/RF Integrated Circuit Design, Electromagnetism, Semiconductor Physics, Integrated Circuit Fabrication, Nanotechnology, Solid-State Sensor, VLSI Circuits, Digital Signal Processing, Communication System

University of Liège, Liège, Belgium

Engineer degree, Electrical Engineering, June 2003
Graduated with the Greatest Distinction 

Intel, Circuit Research Laboratory, Hillsboro (OR), USA

Intern Circuit Designer, Summer 2005

Explored the microelectronic applications of carbon nanotubes
Analyzed the high-frequency characteristics of carbon nanotube circuits through simulations
Authored a conference paper as a result of the internship

National Semiconductor, Portable Power System Group, Santa Clara (CA), USA

Intern Circuit Designer, Summer 2004

Designed at the transistor level in Cadence analog sub-circuits for a single-chip CMOS battery
Wrote Verilog code to implement the digital communication interface
Debugged prototype chips in the lab

IMEC, Mixed-Signal and RF Application Group, Leuven, Belgium

Intern Circuit Designer, January  to June 2003

Designed a CMOS integrated analog filter for a wireless transmitter
Explored architecture options in Matlab
Designed high speed operational amplifiers as the core of the filter, performed the layout of the full filter

Stanford University, Electrical Engineering Department

Co-instructor for the class EE114 – Introduction to Analog MOS Electronics, 2005-2007

Conducted lectures, and supervised undergraduate students during a four-week design project
Held office hours, and provided one-on-one feedback to students. Main instructor: Prof. Robert W. Dutton

Guest lecturer for the class EE218 – Introduction to Nanoelectronics, May 2007

Conducted guest lecture on carbon nanotube interconnects to an audience of graduate students
Main instructor: Prof. H-.S. Philip Wong

Teaching assistant for the class EE309 – Semiconductor Memory, Spring 2006

Provided help to graduate students for weekly homework assignments
Main instructor: Prof. H-.S. Philip Wong

Teaching assistant for the class EE122 – Analog Design Laboratory, Spring 2006

Provided design, fabrication, testing and debugging help to undergraduate students building discrete analog circuits on prototype boards. Main instructor: Prof. Gregory T. A. Kovacs

Co-mentor of a junior PhD student in the Stanford Nanoelectronics Group, Winter 2008

Electronic devices development and integration into proof-of-concept integrated circuits
Analog and RF integrated circuits
Nanotechnology as a tool to explore new applications of integrated circuits (focus on biomedical sensing applications)

Intel Foundation Ph.D. Fellowship (2006-2008)
Belgian American Educational Foundation Fellowship (2003-2004)
Association of Engineers from the University of Liege Best Thesis Award (June 2003)

Native language: French. Country of citizenship: Belgium

·         Prof. Mark A. Reed research group, Yale University, New Haven (CT), USA (December 2007)

·         Laboratory of Micro and Nanoelectronics Devices (Prof. Adrian Ionescu research group), Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland (December 2007)

Journal papers

·         G. F. Close, S. Yasuda, B. Paul, S. Fujita, and H.-S. P. Wong, “1-GHz integrated circuit with carbon nanotube interconnects and silicon transistors,” Nano Letters, vol. 8, pp. 706-709, 2008. [This paper reported on several technology websites: EEtimes.com , Semiconductor.net, …]

·         D. Akinwande, G. F. Close, and H.-S. P. Wong, “Analysis of the frequency response of carbon nanotube transistors,” IEEE Trans. Nanotechnology, vol. 5, pp. 599-605, 2006

Conference papers

·         G. F. Close and H.-S. P. Wong, “Fabrication and characterization of carbon nanotube interconnects,” Proc. IEEE Intl. Electron Devices Meeting (IEDM), pp. 203-206, 2007

·         G. F. Close and H.-S. P. Wong, “Nanostructured materials for interconnects,” Proc. Advanced Metallization Conf. (AMC), pp. 3-13, 2006

·         G. F. Close and H.-S. P. Wong, “Measurability issues in the radio-frequency characterization of carbon nanotubes,” Proc. IEEE Conf. on Nanotechnology (IEEE-NANO), pp. 266-269, 2006