100-nm pMOSFET Fabrication Process
Details of the fabrication process are shown in the figure below. The pMOSFETs were fabricated using a five-mask process incorporating "mix and match" lithography. The gate level was patterned with a scanning probe, while all other lithography levels were patterned with conventional photolithography. LOCOS isolation was performed followed by an arsenic channel implant. The gate oxide thickness was 5.7 nm and the polysilicon thickness was 100 nm. Before gate patterning, the polysilicon was implanted with BF2, followed by a rapid thermal anneal (RTA) to electrically activate the dopants. (The polysilicon must be conductive for hybrid AFM / STM lithography.) To create the gate pad, 50 nm of low temperature oxide (LTO) was deposited and patterned by photolithography. After gate lithography, a 35 nm oxide spacer was formed by LTO deposition and anisotropic RIE. Shallow source / drain junctions were created by BF2 implantation. The final processing steps were: LTO passivation, RTA, furnace anneal, contact photolithography, metallization, and a forming gas anneal.