1. Thermal Engineering of IC Devices and Metallization
Dr. Kaustav Banerjee, Y. Sungtaek Ju, Per G. Sverdrup, and Mehdi Asheghi

Heat generation and conduction influence the reliability of semiconductor devices and interconnects, such as those shown in Figure 1. This is particularly important for smart-power circuits and for devices that must withstand electrostatic discharge (ESD), which can induce rapid melting. Heat transfer is also important for multilevel interconnects in fast logic circuits, for which the trend to larger numbers of levels increases the peak temperature rise induced by Joule heating.

This project provides theoretical and experimental foundations for the thermal engineering of these integrated circuit structures. Solutions to the Peierls Boltzmann transport equation account for the scattering of phonons, which are the quanta of lattice vibrational energy, on interfaces and high-energy electrons and for highly-localized maxima in electron-phonon energy exchange. The transport theory is used to modify the classical heat diffusion energy equation to approximately account for these phenomena in more practical electrical/thermal device simulations. The accuracy of the simulations is improved through the use of thermal property data measured for thin films and interfaces in semiconductor devices and interconnect structures (see Projects 2-5). To establish confidence in the simulations, the facility shown in Figure 1 is used for nanosecond thermometry of devices and interconnects during rapid electrical stressing. Figure 2 compares predictions and transient temperature-field data for a metallization and a high-voltage transistor.

The experiments, modeling, and simulations in this project provide the basis for thermally-rigorous design of semiconductor devices and metallization. This helps with the design of reliable ESD buffer circuitry and multilevel interconnect structures.

Collaboration
Device and Flow Design Group, Texas Instruments. Components Research Group, Intel
Groups of Professors Dutton and Wong, Electrical Engineering Department, Stanford University

Recent Archival Journal Articles

Ju, Y.S., and Goodson, K.E., 1998, "Short-Timescale Thermal Mapping of Microdevices using a Scanning Thermoreflectance Technique," ASME Journal of Heat Transfer, Vol. 120, pp. 306-313.

Ju, Y.S., Käding, O.W., Leung, Y.K. Wong, S.S., and Goodson, K.E., 1997, "Short Timescale Thermal Mapping of Semiconductor Devices," IEEE Electron Device Letters, Vol. 18, pp. 169-171.

Ju, Y.S., and Goodson, K.E., 1997, "Thermal Mapping of Interconnects Subjected to Brief Electrical Stresses," IEEE Electron Device Letters, Vol. 18, pp. 512-514.

Major Review Articles and Book Chapters

Goodson, K.E., and Ju, Y.S., 1999, "Heat Conduction in Novel Electronic Films," Annual Review of Materials Science, in press.

Goodson, K.E., Ju, Y.S., and Asheghi, M., 1998, "Thermal Phenomena in Semiconductor Devices and Interconnects," Microscale Energy Transport, C.L. Tien, A. Majumdar, and F. Gerner, eds., Taylor & Francis, New York, pp. 229-293.

Sponsorship
Semiconductor Research Corporation Contract 98-SJ-461
Texas Instruments Fellow-Mentor-Advisor Program
ONR Grant 96-1-0688 (Young Investigator Award, Electronics Division)
NSF Grant CTS-9624696 (CAREER Award). NSF Grant CTS-9622178