Computer Architecture Paper Reading Group

2004

Day: Thursday

Time: 5-6pm

Place: Gates 392

Each week we will discuss one or two papers. One individual will be chosen to give a brief summary of the papers at the beginning of the meeting before discussion starts. The person responsible for leading the next week’s discussion will jot down notes about the discussion which will then be posted on this web page.

Participants should be prepared to discuss the following for each paper:

1. What is the problem they are trying to solve/indicate/characterize?

2. Why is the problem important/relevant?

3. What are the novel/interesting ideas in this paper?

4. What are the flaws/limitations of this paper?

5. How would you extend this work?

6. How does this paper related to other papers from same/previous discussions?

7. Are there concepts or methods in the paper that are unclear?

Date	Topic	Papers	Discussion Leader	Notes
1/22/04	Multithreading	R. Saavedra-Barrera, D. Culler, T. von Eicken. Analysis of Multithreaded Architectures for Parallel Computing. Proceedings of the 2^nd Symposium on Parallel Algorithms and Architectures (SPAA), Crete, Greece, July 1990.	Christos	Kelly
		Ravi Rajwar, James R. Goodman. Transactional lock-free execution of lock-based programs. ASPLOS 2002: 5-17
1/27/04	Simulation	Timothy Sherwood, Erez Perelman, Greg Hamerly and Brad Calder. Automatically Characterizing Large Scale Program Behavior, In the proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2002), October 2002. San Jose, California	Kelly	Francois
		Roland Wunderlich, Thomas Wenisch, Babak Falsafi, and James Hoe. SMARTS: Accelerating Microarchitecture Simulation through Rigorous Statistical Sampling. International Symposium on Computer Architecture (ISCA), June 2003
2/5/04	Power	A.P. Chandrakasan, S. Sheng, and R.W. Brodersen. Low-power CMOS digital design. IEEE Journal of Solid-State Circuits, Vol.: 27, Issue: 4, April 1992. Pages:473 - 484	Francois	Mattan
		Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Toan Pham, Rajeev Rao, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge, and Krisztián Flautner, Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, in the 36th Annual International Symposium on Microarchitecture (MICRO-36), December 2003
2/12/04	Reliability	Todd Austin, DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design, ACM/IEEE 32nd Annual Symposium on Microarchitecture (MICRO-32), November 1999, received Best Paper Award.	Mattan	Vicky
		L. Spainhower and T. A. Gregg, IBM S/390 Parallel Enterprise Server G5 fault tolerance: A historical perspective, IBM Journal of Research and Development, Vol. 43, Nos. 5/6, 1999, pp. 863-874.
2/19/04	Biocomputing	Seth Copen Goldstein and Mihai Budiu. NanoFabrics: Spatial Computing Using Molecular Electronics. In Proc. 28th Annual International Symposium on Computer Architecture, pp. 178-191, June 2001.	Vicky	Ben
		M. Ogihara, A. Ray, and K. Smith, DNA computation--a shape of computing to come, SIGACT News 28(3), pp. 2-11, 1997.
		M. Ogihara and A. Ray, Biomolecular computing--recent theoretical and experimental advances, SIGACT News , 30(2):22-30, 1999.
2/26/04	Dynamic Compilation	Arnold, M., Fink, S., Grove, D., Hind, M., and Sweeney, P.F., " Adaptive Optimization in the Jalapeno JVM," ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications (OOPSLA'00), Minneapolis, Minnesota, October 15-19, 2000.	Ben
		James C. Dehnert, Brian K. Grant, John P. Banning, Richard Johnson, Thomas Kistler, Alexander Klaiber, and Jim Mattson, " The Transmeta Code Morphing Software:Using Speculation, Recovery, and Adaptive Retranslationto Address Real-Life Challenges," in the Proceedings of the First Annual IEEE/ACM International Symposium on Code Generation and Optimization, 27-29 March 2003, San Francisco, California
3/11/04	Embedded Systems	Bharat P Dave, Ganesh Lakshminarayana, Niraj K Jha. COSYN: Hardware Software Co-Synthesis for Embedded Systems, 34th DAC Anaheim, 1997.	Brandon	Sewook
		F Salice, Del Vecchio, L Pomante, W Fornaciari. Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures, Proceedings of the 2003 ACM symposium on Applied Computing.
4/8/04	Bandwidth and Latency	“Latency Lags Bandwidth”		Samir
4/15/04	Transactions	Hammond et. al. Transactional Memory and Coherence to appear in ISCA 2004.	Samir	Njuguna
		TBA
4/22/04	Synchronization	Ravi Rajwar, James R. Goodman. Transactional lock-free execution of lock-based programs. ASPLOS 2002: 5-17	Njuguna	Rebecca
		Jose F. Martinez and Josep Torrellas. Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications. ASPLOS 2002.
4/29/04	Server / Power	E.N. (Mootaz) Elnozahy, Michael Kistler, and Ramakrishnan Rajamony. Energy-Efficient Server Clusters in Proceedings of the Workshop on Power-Aware Computing Systems, Feb. 2002.	Rebecca
		Charles Lefurgy, Karthick Rajamani, Freeman Rawson, Wes Felter, Michael Kistler, and Tom W. Keller. Energy Management for Commercial Servers IEEE Computer 36(12): 39-48 (2003)
5/6/04	Processor in Memory	A. Saulsbury, F. Pong, and A. Nowatzyk. Missing the Memory Wall: The Case for Processor Memory Integration in Proceedings of the 23rd International Symposium on Computer Architecture, pages 90-- 101, May 1996.
		Yan Solihin, Jaejin Lee, and Josep Torrellas. Automatic Code Mapping on an Intelligent Memory Architecture IEEE Transactions on Computers: special issue on Advances in High Performance Memory SystemsComputer , November 2001.

If you have questions or comments, email either Kelly Shaw (kashaw (at) cs.stanford.edu) or Christos Kozyrakis (christos@ee.stanford.edu).