Enabling Technology:
Neural silicon

Neuromorphic chips were pioneered by Carver Mead in the late eighties, when he developed the first silicon retina at Caltech. Extrapolating the doubling in computer performance that was occurring every eighteen months (Moore’s Law), Mead predicted correctly in 1990 that present-day computers would use ten million times more energy (per instruction) than the brain uses (per synaptic activation). He sought to close this efficieny-gap by building microelectronic circuits based on the brain. Mead succeeded in mimicking ion-flow across a neuron's membrane with electron-flow through a transistor's channel. This should not have come as a surprise: the same physical forces are at work in both cases!

A silicon neuron is an analog electronic circuit of transistors that mimic a real neuron's repertoire of ion-channels.

Instead of designing different electronic circuits to emulate each of a wide variety of ion-selective protein pores that stud neurons' membranes, as Mead did in his silicon retina, we came up with a versatile silicon model. This was possible with as few as eight transistors—thanks to the physical analogy. Some ion channels open quickly when the voltage across the membrane is high, others open slowly when the voltage is low, and everything in between. Nevertheless, the fraction that is open follows a sigmoid-curve as the membrane voltage changes and the time it takes to reach this new level follows a bell-curve. Our silicon model captures this behavior: computer-controlled bias voltages fit its "curves" to the desired ion-channel type. Its compact size allows millions of distinct ion-channel populations to be modeled with a single chip.

Recent breakthroughs in neuromorphic engineering make it possible to combine analog's real-time operation with digital's programmability, reaping the best of both worlds.

Instead of hardwiring the silicon neurons together, as Mead did in his silicon retina, we assigned them (and their synaptic targets) unique addresses. Every time a spike occurs, the chip outputs that neuron’s address. This address points to a memory location (RAM) that holds the synaptic target’s address. When this address is fed back into the chip, a post-synaptic potential is triggered at the target; assigning multiple memory locations to a neuron makes multiple synaptic targets possible. Encoding, translating, and decoding an address happens fast enough to route several million spikes per second, allowing a million connections to be made among a thousand silicon neurons. These softwires may be rerouted simply by overwriting the RAM’s look-up table, making it possible to specify any desired synaptic connectivity.

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