Ben Varkey Benjamin
Circuits: Neurons

Personal Background

I have always wanted to build something novel and tangible. I need two things to do so: inspiration (what to build) and knowledge (how to build). Growing up amidst the tremendous technological growth in the late 20th and early 21st century, I picked Electronics and Communications Engineering as my undergraduate major in the hope of finding inspiration, and of course, know-how. After four years, I realized I knew very little (albeit, about a lot) to build anything and so I had to pick a subdiscipline to delve deeper.

Ben Varkey Benjamin

As luck would have it, I got an offer from a VLSI services company, a job that introduced me to chip design, a field I would explore during my three years in the industry. I was exposed to various subdisciplines: front-end (RTL/gate) design, physical design, back-end (circuit/layout) design and so on. Among these, I was fascinated by analog and mixed-signal design, which I wanted to learn more about, and so I enrolled in graduate school at Stanford with this intention.

I had hoped to finally settle on my chosen field, however, the multidisciplinary academic environment at Stanford opened up new possibilities and once again I was at a crossroads. I found out about a course Prof. Boahen offered on large-scale modeling of cortical networks. I didn't have any background in Neuroscience, but the brain had always been as a source of inspiration for me. Now, this alone wouldn't have made me take the class, but, Prof. Boahen had a neuromorphic chip that I would get to use in the class. This piqued my interest—here was something novel and tangible and clearly this was an inspired design. I joined the lab soon after, with the goal of building something, drawing from the endless stream of inspiration the brain offers.

Research Goals

My current focus is on devising strategies for using deep submicron devices for neuromorphic designs, strategies that could be migrated to new devices as they become available. Analog computation is cheap in terms of power. However, in deep sub-micron processes, the design overhead to make traditional analog designs work in the face of leakage and mismatch is becoming prohibitive. We need a design framework that would ensure a working design in the face of issues like temperature dependence and mismatch. This framework will still be useful when newer devices with better electrostatic control than planar MOSFETs become available.

Project Status

Synapse Diffusor Profile

Neurogrid's Local Arbor Mechanism: A spike delivered to a silicon neuron in the center elicits postsynaptic potentials in neighboring neurons that decay exponentially from the center, starting with the six nearest neighbors. The decay is less abrupt as the programmable space-constant increases (left to right, top to bottom).

To expand the quadratic/cubic leaky integrate and fire (LIF) neuron's repertoire of behaviors, I designed a resonator neuron, which exhibits a Hopf bifurcation. As this design could also be configured to exhibit a saddle-node bifurcation, it realizes richer neuronal behavior while having almost the same footprint as the LIF neuron.

I also briefly worked on porting CMOS neuron designs to silicon nanowires. Then I worked on Neurogrid, testing, characterizing and calibrating the chips, while also helping with software development for interfacing Neurogrid with the PC. While working on Neurogrid, I came across a few issues that led me to my current focus.

Neurogrid uses PTAT biases (proportional to absolute temperature) to compensate for temperature. However, not all its circuits take advantage of this to display temperature invariant behaviors, which result in issues like temperature-dependent firing rates. Neurogrid uses minimalist circuits, which are clever but result in second order effects more visible in deep-submicron technologies. For instance, parasitic capacitors dump charge, which results in a fast transient that deviates from the designed time constant. There are also uncompensated diode drops that make the design less scalable with decreasing supply voltage. I am currently working on a systematic approach to low-power designs that will help minimize these issues and more.

Publications

ID Conference Full Text
C40
B V Benjamin, J V Authur, P Gao, P Merolla and K Boahen, Superposable Silicon Synapse with Programmable Reversal Potential, International Conference of the IEEE Engineering and Medicine in Biology Society, pp 771-4, 2012.

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ID Journal Full Text
J36 P Gao, B V Benjamin and K Boahen, Dynamical system guided mapping of quantitative neuronal models onto neuromorphic hardware, IEEE Transactions on Circuits and Systems. Vol 59, no 10, pp 2383-94, Oct 2012
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Patents

ID Patent Full Text
 
B V Benjamin, Technique for generation of load-slew indices for circuit characterization, US Patent: 8352901, 2013
 
 
B V Benjamin, Technique for digital circuit functionality recognition for circuit characterization, US Patent: 7899660, 2011