EE 410 - Process and Device Modeling report

Each student will simulate the EE410 CMOS process and write a report. You may consult with other students in your group or in the class, however, the simulations and other calculations should be done by each student individually and the report is to be written also by each student individually.

Content

Less than 10 pages of main body. It should be written similar to a paper published in a Journal. Any supporting material should go in an appendix.

Simulations

(by SUPREM, etc.) and calculations of the structures (e.g. thickness, doping profile, ..........) and electrical parameters (e.g. sheet resistance, threshold voltage, ..........) that should result from the process flow. Organize the report in the following format.

I) Introduction

Include a short overview of the process and the structure

II) Analytical calculations (by hand)

a) Field and gate oxide thicknesses

b) Ion implant profiles

c) Junction depths

d) Sheet resistance of junctions and poly-Si gate

e) Threshold voltages

III) SUPREM Simulations on the same topics as in II)

IV) Comparison and Discussion

A table showing SUPREM values and hand calculated values and a discussion on discrepancies.

V) Conclusion

VI) References

Schedule

1 copy of the paper will be due on 2/9/2009

Grading

The paper will be graded according to the following guidelines :

Completeness of information 10%

Quality of presentation 10%

Innovations and others 5%