EE410 : Integrated Circuit Fabrication Laboratory

Winter 2008-09, Prof. Krishna Saraswat

Announcements
Course description
Class schedule
Handouts
Teaching staff
Grading

Announcements

The first organizational meeting of EE410 will take place on Wednesday, January 7, in CISX 101 (auditorium) at 12:00pm. In this meeting we will divide the class into groups. The Class size will be limited to 20 students (4 groups of 5 students each). You are expected to be available for one full morning or afternoon for the laboratory session during Tuesdays - Thursdays. There will be no lab sessions on Mondays or Fridays. If you miss this meeting your chances of taking the class will be diminished as the class size is limited to 20 students.

There will be about 6 one hour meetings through the quarter including the course organization meeting. Please bring your availability schedule with you to this meeting.

There will be a second meeting on Friday, January 11 at 12 pm in CISX 101 . In the second meeting a short lecture will be given on safety in the CIS fabrication facility followed by a safety tour of the SNF. If you miss this meeting you won't be allowed to take the course unless you have taken the CIS safety class earlier. If you have already taken the CIS safety class send me the date you took it.

Before you take the lab safety tour you are required to view the video material online at your own leisure. There are three videos at: http://snf.stanford.edu/Access/LabClass.html. There is a manual at the same site. Read the manuals and take the safety test before the Friday tour (which are included in the training folders to be given to you in the first meeting). Videos, manual and test take about 3-4 hours to complete

Check your group assignment by clicking here after Thursday, January 8.

Course description

The course involves CMOS process simulation using SUPREM, laboratory fabrication, testing and characterization of silicon gate CMOS devices and simple integrated circuits. Emphasis is on the practical aspects of IC fabrication, including silicon wafer cleaning, photolithography, etching, oxidation, diffusion, ion implantation, chemical vapor deposition, physical sputtering and wafer testing. Specifically the course is diveded in three parts:

1. CMOS fabrication for silicon integrated circuits.

2. CMOS process simulation using SUPREM.

3. Device testing and characterization.

4 units for CMOS (3 units option is possible), Letter grade only.

Class size will be limited to 20 students divided into 4 groups. Each group will be led by a TA. Each group will meet once a week for an entire morning or afternoon. Preference will be given to those who are planning to use the IC Lab fabrication facility for their research.

Prerequisites:

EE212 and EE216 or equivalent required.

Text:

None. Notes will be provided.

References:

1. EE212 text and notes, Plummer, Deal and Griffin.

2. VLSI Technology, Sze.

3. Silicon Processing for the VLSI Era, Vol. 1 & 2, Wolf & Tauber.

4. Atlas of IC Technologies, Maly

5. Semiconductor Material and Device Characterization, Schroder.

6. Pierret, "Semiconductor Device Fundamentals", Addison-Wesley.

7. Muller and Kamins, "Device Electronics for Integrated Circuits", Wiley.

Class schedule

Lecture:

About 6 meetings will take place through the quarter.

1. "Course organization meeting" - 1/7/2009, Wednesday, 12:00 - 1:00 PM, CISX 101.

2. "Safety training" Friday, 1/9/2009, 12 - 2 PM, CISX 101

3. "Cleaning and clean Processing Techniques" Friday, 1/16/2009, 12 - 1 PM, CISX 101

4. "Process simulation using SUPREM" Friday, 1/23/2009, 12 - 1 PM, CIS 101

5. "Description of the test structures in EE410 mask sets", 2/13/2009, 12 - 1 PM, CISX 338

6. "Comparison of EE410 CMOS process with industry standard processes", 2/27/2009, 12 - 1 PM, CISX 338

Lab:

4 to 6 hours per week of laboratory work in one morning or afternoon on a weekday by arrangement.

Handouts

Electronic versions of some handouts will be available in Adobe's increasingly popular PDF format. Viewing and printing the handouts and assignments will require the use of Adobe's Acrobat Reader, the latest verison of which can be downloaded for FREE! from Adobe's Web Page. Click here to travel there. Additional course notes will be provided during the lectures.

Handout #1 on Introduction to EE410

Handout #2 on Cleaning and Contamination

Handout #3 on Process Simulation

Handout #4 on CMOS-LOCOS Manual

Handout #5 on Running TSUPREM on campus computers

Handout #6 on EE410 CMOS Process

Handout #7 on Test Structures and Testing

Handout #8 on Advances in MOS Technology