EE410 : Integrated Circuit Fabrication Laboratory

Winter 2007-08, Prof. Krishna Saraswat

Announcements
Course description
Class schedule
Handouts
Teaching staff
Grading

Announcements

The first organizational meeting of EE410 will take place on Wednesday, January 9, in CISX 101 (auditorium) at 12:00pm. In this meeting we will divide the class into groups. The Class size will be limited to 20 students (4 groups of 5 students each). You are expected to be available for one full morning or afternoon for the laboratory session during Tuesdays - Thursdays. There will be no lab sessions on Mondays or Fridays. If you miss this meeting your chances of taking the class will be diminished as the class size is limited to 20 students.

There will be about 6 one hour meetings through the quarter including the course organization meeting. Please bring your availability schedule with you to this meeting.

There will be a second meeting on Friday, January 11 at 12 pm in CISX 101 . In the second meeting a lecture will be given on safety in the CIS fabrication facility. If you miss this meeting you won't be allowed to take the course unless you have taken the CIS safety class earlier. If you have already taken the CIS safety class send me the date you took it.

Check your group assignment by clicking here after Thursday, January 10.

Course description

The course involves CMOS process simulation using SUPREM, laboratory fabrication, testing and characterization of silicon gate CMOS devices and simple integrated circuits. Emphasis is on the practical aspects of IC fabrication, including silicon wafer cleaning, photolithography, etching, oxidation, diffusion, ion implantation, chemical vapor deposition, physical sputtering and wafer testing. Specifically the course is diveded in three parts:

1. CMOS fabrication for silicon integrated circuits.

2. CMOS process simulation using SUPREM.

3. Device testing and characterization.

4 units for CMOS (3 units option is possible), Letter grade only.

Class size will be limited to 20 students divided into 4 groups. Each group will be led by a TA. Each group will meet once a week for an entire morning or afternoon. Preference will be given to those who are planning to use the IC Lab fabrication facility for their research.

Prerequisites:

EE212 and EE216 or equivalent required.

Text:

None. Notes will be provided.

References:

1. EE212 text and notes, Plummer, Deal and Griffin.

2. VLSI Technology, Sze.

3. Silicon Processing for the VLSI Era, Vol. 1 & 2, Wolf & Tauber.

4. Atlas of IC Technologies, Maly

5. Semiconductor Material and Device Characterization, Schroder.

6. Pierret, "Semiconductor Device Fundamentals", Addison-Wesley.

7. Muller and Kamins, "Device Electronics for Integrated Circuits", Wiley.

Class schedule

Lecture:

About 6 meetings will take place through the quarter.

1. "Course organization meeting" - 1/9/2008, Wednesday, 12:00 - 1:00 PM, CISX 101.

2. "Safety training" Friday, 1/11/2008, 12 - 2 PM, CISX 101

3. "Cleaning and clean Processing Techniques" Friday, 1/25/2008, CIS 101

4. "Process simulation using SUPREM" Friday, 2/1/2008 CISX 316

5. "Description of the test structures in EE410 mask sets"

6. "Comparison of EE410 CMOS processes with industry standard processes, "

Place, Date and time to be announced for the remaining lectures

Lab:

4 to 6 hours per week of laboratory work in one morning or afternoon on a weekday by arrangement.

Handouts

Electronic versions of some handouts will be available in Adobe's increasingly popular PDF format. Viewing and printing the handouts and assignments will require the use of Adobe's Acrobat Reader, the latest verison of which can be downloaded for FREE! from Adobe's Web Page. Click here to travel there. Additional course notes will be provided during the lectures.

Handout #1 on Introduction to EE410

Handout #2 on CMOS manual

Handout #3 on CMOS run sheet

Handout #4 on Safety given in the class

Handout #5 on Cleaning and Contamination

Handout #6 on Using TSUPREM-IV

Handout #7 on Process and Device Simulations

Handout #8 on Test Structures

Handout #9 on Testing Policies Procedures

Handout #10 on Device Testing: Appendix A given in the class

Handout #11 on Device Testing: Appendix B given in the class

Handout #12 on CMOS II manual: Appendix B Pad Assignments