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EE384X: Packet Switch Architectures - I

3 units, Winter 2008


Nick McKeown, Balaji Prabhakar

Lectures: Mon Wed 11:00 AM - 12:15 PM, CummsArt 4

Review session: Friday 11-12:15, Packard 277

Final Exam: Thursday, March 20, 8:30am-11:30am


Course Description

384X Packet Switch Architectures I: The theory and practice of designing packet switches, such as Internet routers, Ethernet switches and ATM switches. Introduction: evolution of switches and routers. Output scheduling: motivation for providing bandwidth and delay guarantees; fairness; active queue management and packet dropping schemes. Switching: example architectures, performance metrics; unicast switching: blocking phenomena, connections with bipartite graph matching, practical algorithms; unicast switching with speedup; multicast switching. Address lookup: exact and longest prefix matches, performance metrics, hardware and software solutions. Packet classifiers: for firewalls and policy-based routing; graphical description; Theoretical complements: basic queuing models, graph matching algorithms, stability through Lyapunov functions, fluid models.

Prerequisites: EE284/CS244a and familiarity with probability (for example, from EE178, EE278, or Statistics 116.)
Recommended: CS161

Note: EE384X is the first of a two part course being held over Win, Spr. The syllabus for the two courses are:
EE384X:
Part I: Output Queued Switches (Emphasis on Deterministic Analysis)
Part II: Input Queued Switches (Emphasis on Probabilistic Analysis)
EE384Y:
Part III: Other Switch Architectures
Part IV: Other Switch Functions


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