Course description: EE382A provides in-depth coverage of fundamental architecture and implementation techniques for modern processor chips. It covers topics such as advanced pipelining, superscalar execution, out-of-order processing, speculative execution, VLIW, data parallelism, multithreading, graphics processors, and multi-core chips. The students will become familiar with complex trade-offs between performance-power-complexity and the common techniques for addressing the challenges in historical and modern processors. A central part of EE382A is a group project on an open research question. EE382A assumes a solid background on basic computer organization including instruction set design, pipelining, caching, virtual memory. EE108B, or an equivalent class, is a prerequisite. EE382a touches on the topic of advanced caching hierarchies covered in EE282. However, EE282 is not a prerequisite.
Lecture: Monday & Wednesday, 11am - 12.15pm, Hewlett Teaching Center room 101.
Instructors: Christos
Kozyrakis (christos@ee.stanford.edu)
and John
Shen (??@stanford.edu)
Gates Hall Room 304, (650) 725-3716, office hours: Mo 10-11am; Wed 1.30-2.30pm
Teaching Assistant: Davide Signorelli (signorda@stanford.edu)
office TBD, office hours TBD
Note on office hours: visit the class webpage regularly for the last office hours schedule.
Administrative Support: Teresa Lynn (tlynn@csl.stanford.edu), 305 Gates Hall, (650) 724-6540
Class Webpage: http://eeclass.stanford.edu/ee382a/
Visit the web page regularly. All the handouts and announcements will
be available on-line. You will need to register with the webpage in
order to obtain on-line access to grades and homework
solutions. Follow the “students” link on the left bar of
the page. Registration will be open a few days after the
beginning of the quarter. All other material will be available to the
public from the webpage.
Class Mailing-list: Registered students will be automatically added to the class-mailing list. The list will be used only for announcements by the class staff. Announcements will also be available at the class webpage and bulletin board.
Policy on Questions & Emails: The preferred method for asking questions is through the bullettin board, accessible through the class webpage. We will check the newsgroup regularly, especially close to assignment deadlines. All answers will be posted on the newsgroup and will be mailed to the person that posted the original question. When posting a question to the newsgroup, make sure you use an appropriate subject. For example, if your questions refers to the definition of memory latency in problem 2 of homework 1, an appropriate subject would be "HW1, problem 2: definition of memory latency".
Before posting a question on the bulletin board check to see if this question has already been answered. We will not answer the same question multiple times! Take advantage of the search capabilities of newsgroup viewers such as Eudora and Outlook Express. In addition, check the FAQ section of the webpage description for homework assignments.
For questions that are not appropriate for posting to the bulletin board, you can email the TA or the instructor directly. Write “ee382A” at the beginning of the email subject. Note that grades are accessible through the class web page (registration required).
Handouts: All the handouts will be available in electronic
form at the class web page. Paper handouts will be available at the
classroom and in a lobby filling cabinet at Gates Hall 3rd floor. The
lecture notes will be typically posted on the webpage a couple
of hours before the lecture. Paper copies will typically be
available in the classroom.
Prerequisites & Registration: EE108b (Digital Systems
II) or EE182 (Computer Organization & Design) or equivalent at
other institutions. You are expected to understand basic processor
core design (pipelined processors) and advanced topics on system
architecture (cache hierarchies, memory systems, IO, OS
support). EE282 and CS315a are not required prerequisites.
Registration to EE382A is limited to 30 students. The class is
appropriate for Ph.D. students working in computer systems
(architecture, compilers, OS, design, ...) and advanced practitioners. All
students will be have to receive final approval from the instructor
based on a questionnaire and HW1 that will be given to you after ath
the first lecture. Same rules apply for all students
(undergraduate or graduate).
Required Textbook: J.P. Shen and M. Lipasti, "Modern Processor Design: Fundamentals of Superscalar Processors", 1st edition, McGraw-Hill.
Optional Textbooks: J. Hennessy and D. Patterson (H&P), "Computer Architecture: a Quantitative Approach", 4th edition, Morgan Kaufmann Publishers; D. Patterson and J. Hennessy (P&H), "Computer Organization and Design: the Hardware/Software Interface", 4th edition, Morgan Kaufmann Publishers. We will use certain portions of these books. Copies of these books are available at the Engineering library.
Additional Reading: On every class topic, there will be a few research papers to read. Papers will be clearly marked as either required or optional reading. Required readings will provide complementary information to the textbooks. For every required paper you will submit a 1 page summary before the beginning of the next lecture. Optional readings will identify the latest developments and trends on the topic. Optional reading will not be included in the exams. Submission instructions:
Discussion Sessions: There will be several review session. All session will be held on Fridays (room TBD, time TBD). The exact schedule will be announced on the webpage.
Exams: There will be a single exam on Fri 11/13th (time TBD, room TBD). It will cover all lectures up to that point. Bring a calculator. Alternative exam times will not be available to any students. If you cannot take the exam on the specified date, you should probably not take the class. There will be no exam during the finals period.
Homework: There will be 3 homework sets. All assignments are due by 5.00pm on the dates indicated in the schedule. Solutions to homework sets will become available the same evening.
Late Assignments and Regrading: All deadlines are final. No extensions, no exceptions. Late assignments will not be accepted and the grade “zero” will be given automatically. Requests for regarding must be submitted within a week from grade assignment date. Submit a note that describes the specific grading complaint and your assignment manuscript. However, regrading will affect the whole homework/exam (not just one question) and can lead to a lower grade than the original one.
Project: EE382a includes a project on an open research question related to computer architecture. The project will include a proposal, a status review, a final presentation, and a final paper.
Collaboration: You will work on homework and project in groups of 3 students. Groups with less than 3 students will only be allowed after the instructor's permission. In general, collaboration is encouraged subject to the following guidelines:
You should also read the extensive note about the honor code and accepted forms of collaboration in general.
Grading (tentative):