Table of ContentsEE382 Processor Design Concurrent Processors Speedup SIMD processors SIMD processors Vector Processors Vector Processor Architecture Vector Processor Operations Vector Processor Storage Vector Function Pipeline VP Concurrency Vector Processor Organization Vector Processor Summary Vector Memory Mapping Vector Memory Modeling _-Binomial Model Finding _opt TBF Example Inter-Instruction Bypassing Vector Processor Performance Metrics High-Bandwidth Interleaved Caches Example VP vs Multiple Issue Summary |
Author: Susan Gere
Email: gere@stanford.edu |