In the area of chip design, advances in technology have far outstripped advances in design productivity. In order to get the largest system-on-chip designs to market on time, companies have been forced to re-use large pieces of pre-existing designs. The use of such intellectual property (IP) cores has led to a new problem: that of IP core integration. In this talk, I will introduce the MicroNetwork, a new solution for system-on-chip integration. I will explain what a MicroNetwork is, how it is used, and what its advantages are. I will also go into the details of Sonics' first MicroNetwork implementation: the SiliconBackplane.
About the speaker:
Wolf-Dietrich Weber is the Director of Architecture at Sonics Inc, a venture-funded company dedicated to accelerating system-on-chip design. He received his Ph.D. in Electrical Engineering from Stanford University in 1993. While at Stanford, he was part of the DASH multiprocessor project and sat through many EE380 seminars. After leaving Stanford, Dr. Weber worked at HAL Computer Systems and Fujitsu System Technologies where he was part of the team that designed and implemented the Synfinity interconnect architecture for large-scale multiprocessors. Dr. Weber co-authored the book "Scalable Shared-Memory Multiprocessing" published by Morgan Kaufmann.
Contact information:
Wolf-Dietrich Weber
Sonics, Inc.
2440 W. El Camino Real, Suite 620
Mountain View, CA 94040
(650) 938-2500 ext. 122
(650) 938-2577
lupus@sonicsinc.com