The focus of this talk is on IC manufacturing process variability which, next to power consumption, is one of the two major challenges facing chip designers in the next decade. More specifically how to design circuits for yield in the presence of manufacturing variations will be discussed.
Unlike the challenges found in power management which can be handled at the system, architectural, and logic levels of the design, design for yield must be tackled primarily at the circuit level. A clear understanding into the variability governing the manufacturing process and its impact on circuit functionality is the key. Ignoring variability may result in designs with low or suboptimal yields or below target speed distributions, factors that translate into increased cost.
The challenge of designing under process variability is not new. While in the past it has been restricted to mostly analog circuits, in modern submicron technologies nearly all circuits, digital or analog, are impacted by it. Three reasons for this phenomenon are identified: 1) The high levels of integration that makes possible billions of transistors per chip (i.e., Moore's Law), 2) The ever shrinking device geometries - down to atomic dimensions, and 3) The ultra low Vdd levels required for power management.
In this talk the use of statistical methods in circuit design will be presented. The major sources of IC manufacturing process variability will be explained first. Then its impact on circuit functionality and timing will be analyzed. Statistical methods using Monte Carlo will be discussed and several examples will be provided. Finally test structures designed to measure process variability in Silicon and test data in a 65nm CMOS process will be presented.
Slides:
Download the slides for this talk in PDF format.
About the speaker:
Fabian Klass has over 12 years of experience in microprocessor physical design. He is currently a Director of Technology and Manufacturing at P.A.Semi (http://www.pasemi.com) which he joined in June 2004. In his current role, he has focused on design for yield by developing statistical methodologies applied to circuit design and timing. He is also in charge of foundry relationships and product engineering at P.A.Semi.
Prior to this, Dr. Klass was at Sun Microsystems where he was the chief circuit engineer for the next-generation dual-core UltraSPARC IV+ microprocessor. During his tenure at Sun he made key contributions to four generations of SPARC microprocessors, focusing on circuit techniques, design methodologies, and design for manufacturing. Dr. Klass also taught VLSI design courses at Santa Clara University, CA, in 2000-01. During 1992-1994 he was a visiting scholar at the Electrical Engineering department of Stanford University, where he did research on wave-pipelining.
Dr. Klass published over a dozen technical papers and holds 25 patents, with 6 more pending. He earned a Ph.D. in Electrical Engineering from the Delft University of Technology in The Netherlands, a MSEE from the Technion in Israel, and a BSEE from the Tucuman National University in Argentina.
Contact information:
Fabian Klass, Ph.D. , Director, Technology & Manufacturing
P.A. Semi Inc.
3965 Freedom Circle
Santa Clara, CA 95054
(408) 200-4539
klass@pasemi.com