High-Speed Asynchronous Standard-Cell Design
using Single-Track Full Buffers

Peter Beerel
EE Systems, USC

This talk presents the single-track full-buffer (STFB) circuit family for high-speed semi-custom asynchronous design. It presents the design of a STFB standard-cell library using TSMC 0.25 um technology that is now freely available through the MOSIS Educational Program. We discuss the design of a completed STFB-based demonstration chip that uses this library along with a standard commercial back-end design flow. The chip contains a 64-bit prefix adder and related test logic with 260,000 transistors. It was fabricated and successfully tested. We present the measured results that demonstrate correct operation with a peak throughput of 1.45 GHz.

The talk covers the STFB transistor-level cell design, sizing, short-circuit current analysis, and timing analysis. STFB-based designare notable in that they require no explicit control outside of the datapath and the data is 1-of-N encoded. With a forward latency of 2 transitions and a cycle time of only 6 transitions for most pipeline stages, STFB designs can operate up to 2 GHz using the MOSIS TSMC 0.25 um technology. This is approximately three times faster than all known quasi-delay-insensitive (QDI) templates and has less timing assumptions than ultra-high-speed GasP bundled-data circuits. In particular, we demonstrate the STFB timing assumptions can be easily met in a standard-cell environment by controlling maximum wire length.

The talk concludes with a preview of a new static single-track full buffer family for robust operation in deeper submicron technologies, a back-annotation flow for STFB-based circuits, and plans for our next demonstration chip.

About the speaker:

Dr. Beerel received his B.S.E. degree in Electrical Engineering from Princeton University, Princeton, NJ, in 1989 and his M.S. and Ph.D. degrees in Electrical Engineering from Stanford University, Stanford, CA, in 1991 and 1994, respectively. He joined the the Department of Electrical Engineering--Systems at USC in 1994, where he is currently an Associate Professor. He is also the Faculty Director of Educational Programs at the Mark & Mary Stevens Institute of Technology Commercialization. He has been a member of the technical program committee for the International Symposium on Advanced Research in Asynchronous Circuits and Systems since 1997, was Program Co-char for ASYNC'98, and is now on the Steering Committee. His research interests include a variety of topics in CAD and asynchronous VLSI design. Dr Beerel has consulted for Intel in the area of asynchronous design, Trellisware in the area of communication hardware design, Yuni Networks and AMCC in the area of network chip analysis and verification, and Fulcrum Microsystems in the area of asynchronous design, verification, and CAD. He was on leave of absense from USC between June 2002 to September 2004 during which time he was Vice-President of CAD and Verification at Fulcrum. Dr. Beerel was a recipient of an Outstanding Teaching Award in 1997 and the Junior Research Award in 1998, both from USC's School of Engineering. He recieved a National Science Foundation (NSF) Career Award and a 1995 Zumberge Fellowship. He was also co-winner of the Charles E. Molnar award for two papers published in ASYNC'97 that best bridged theory and practice of asynchronous system design and was a co-recipient of the best paper award in ASYNC'99.

Contact information:

Peter Beerel
Email: pabeerel@usc.edu