For more than 30 years, the computer industry has relied heavily on the ability to increase the speed of the MOS silicon tranistor. This increase in speed has come largely through the downward scaling of the physical dimensions of the device. At the same time, the doping concentrations in the device have had to increase to maintain good electrical isolation and low resistance.
This talk will discuss some of the potential problems in the continued conventional scaling of the MOS device. Issues in scaling both physical thicknesses as well as dopant concentrations will be addressed. In addition, current methods to improve transistor performance through source/drain and well engineering will be explained.
About the speaker:
Paul Packan currently manages the process and device modeling group at intel Corporation in Hillsboro, Oregon. His primary interests are in the simulation and development of process technologies. He has been involved in the development of the past three technology generations at Intel Corporation. Prior to Intel Corporation, Packan spent two years working in the area of bipolar transistor design at Seimens, A.G. in Munich Germany. Packan received his BS degree in electrical engineering from the University of Washington and is M.S. and Ph.D. degrees in electrical engineering from Stanford University in the area of silicon defect and dopant diffusion modeling.
Contact information:
Paul Packan
5200 NE Elam Young Pkwy
Hillsboro, OR 97124
(503) 613-9869
(503) 613-9850
paul.a.packan@intel.com