Nov 13,1996
Yale Patt, University of Michigan
Toward 10 IPC Processors - The Instruction Bandwidth Problem

Speaker: Yale Patt, University of Michigan

Subject: Toward 10 IPC Processors - The Instruction Bandwidth Problem

Abstract:

Process technology promises 100 million transistors on a chip by the turn of the century and 1 billion transistors not long after that. Our objective is to harness them in behalf of a highest performing uniprocessor on a chip. Our current target (until we find out we are being too conservative) is a 10 IPC processor. To get there requires two things: delivering much larger instruction bandwidth and consuming that bandwidth. This talk will deal with some global thoughts about the appropriate use of 100 million transistors on a chip, and some specific remarks on what we are doing to deliver larger amounts of instruction bandwidth. Branch prediction, for example, is a necessary but not sufficient element of the solution to the instruction bandwidth problem.

Biography:

Yale Patt is a Professor of Electrical Engineering and Computer Science at the University of Michigan. He is a Fellow of the IEEE, a recipient of the Eckert-Mauchly Award (1996) and the Emanuel Piore Award (1995) and numerous other awards. The research he and his students have done has left an indelible mark on most of today's high performance microprocessors. He is an alumnus of the Computer Systems Laboratory (then the Digital Systems Laboratory) receiving his Phd in 1966. -dra

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