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Class Notes
Handout 1. Same as the course info on this web page
Handout 2. Trends in Integrated Circuits Technology
Handout 3. MOS Gate Dielectric Technology
Handout 4. Shallow Junctions
Handout 5. Ohmic Contacts
Handout 6. Interconnect Scaling
Handout 7. Power Modeling
Handout 8. Interconnect Thermal Modeling
Handout 9. Interconnect Scaling Thermal Issues
Handout 10. How to use TSUPREM4 (Tutorial)
Handout 11. Silicides
Handout 12. AluminumInterconnect Technology
Handout 13. Copper Interconnect Technology
Handout 14. Device Isolation Technology
Handout 15. Deposition and Planarization Technology

Lecture Slides
Trends in Integrated Circuits Technology
MOS Gate Dielectric Technology: Part 1
MOS Gate Dielectric Technology: Part 2
Shallow Junctions/Ohmic Contacts
Silicides & Metal gates
Interconnect Scaling
Aluminum Interconnect Technology
Copper Interconnect Technology
Low-K Dielectrics
Future Interconnect Technology
Future Devices part 1
Future Devices part 2
Future Devices part 3

Sample Exam
1. Exam Example 1
2. Exam Example 2

Useful Publications

General Technology Trends
1. Plummer and Griffin, "Material and Process Limits in Silicon VLSI Technology", IEEE Proceedings, March 2002.
2. Doyal et al., "Transistor Elements for 30nm Physical Gate Length and Beyond", Intel Technology Journal, May 2002
3. P. Wong, et al., "Nanoscale CMOS", IEEE Proceedings, April 1999.

Gate Dielectric
1. Momose, et al., "Feasibility of 1.5-nm Gate Oxide", IEEE Trans. Electron Dev., MARCH 1998.
2. Gupta et al., "Conduction in Gate Oxide", IEEE Electron Dev. Lett., Dec. 1997.
3. Schuegraf and Hu, "A Model for Gate Oxide Breakdown", IEEE Trans. Electron Dev., May 1994.
4. Yang and Saraswat, "Stress Effects in Gate Oxide", IEEE Trans. Electron Dev., April 2000.
5. Bhat et al., "NO Nitrided Gate Oxide", IEEE Trans. Electron Dev., May 1995.
6. Kim et al., "Nitride/Oxide Gate Dielectric", IEEE Trans. Electron Dev., May 1995.
7. Wilk et al., "High-k gate dielectrics", J. Applied Physics, May 2001.
8. Robertson, "High dielectric constant oxides", Eur. Phys. J. Appl. Phys. 28, 265Š291 (2004).

Shallow Junctions
1. Kim, Park and Woo, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime", Part I: Theoretical Derivation", IEEE Trans. Electron Dev., March 2002.
2. Kim, Park and Woo, "Advanced Model and Analysis of Series Resistance for CMOS Scaling Into Nanometer Regime", Part II: Quantitative Analysis", IEEE Trans. Electron Dev., 1996.

Gate Electrode
1. Mann, et al.,, "Silicides and Local Interconnects.....", IBM J. Res. & Dev. July 1995.
2.Yeo, King, and Hu, "Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology", J. Appl. Phys., Vol. 92, No. 12, 15 December 2002.

Device Isolation
1. P. Smeys, "Exerpts from PhD Thesis", Stanford Univ. March 1996.

Interconnect
1. Havemann et al., "High-Performance Interconnects: An Integration Overview", IEEE Proceedings, May 2001.
2. A. Loke, "Process integration issues of low-permittivity dielectrics With copper for high-performance interconnects", Chapter 1 from PhD Thesis, Stanford Univ. March 1999.
3.A. Loke, "Process integration issues of low-permittivity dielectrics With copper for high-performance interconnects", Chapter 2 from PhD Thesis, Stanford Univ. March 1999.
4. A. Loke, "Process integration issues of low-permittivity dielectrics With copper for high-performance interconnects", Chapter 3 from PhD Thesis, Stanford Univ. March 1999.
5. P. Kapur, et al., "Technology and Reliability Constrained Future Copper Interconnects“Part I: Resistance Modeling", IEEE Trans. Electron Dev., 1996.
6. P. Kapur, et al., "Technology and Reliability Constrained Future Copper Interconnects“Part II: Performance Implications", IEEE Trans. Electron Dev., 1996.

Strained-Silicon Technologies
K. Rim, et. al., "Enhanced Hole Mobilities in Surface-channel Strained-Si p-MOSFETs", IEEE IEDM 1995
K. Rim, et. al., "Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFETs", IEEE Trans. Electron Dev. 2000
T. Ghani, et. al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors", IEEE IEDM 2003
S. Thompson, et. al., "A Logic Nanotechnology Featuring Strained-Silicon", IEEE Electron. Dev. Lett., April 2004

Future Technologies
P. Wong, "Beyond the Conventional Transistor", IBM J. Res. & Dev. MARCH/MAY 2002.
J. Hutchby, et. al., "Extending the Road Beyond CMOS", IBM J. Res. & Dev. MARCH/MAY 2002.
Saraswat Group, "3D Integrated Circuits, Proc. IEEE, May 2001.
D. Miller, "Rationale and Challenges for Optical Interconnects to Electronic Chips", Proc.IEEE, June 2000.
A. Naeemi, et al., "Performance Comparison between Carbon Nanotube and Copper Interconnects for GSI", IEDM 2004.

Power
P. Kapur, et al., "Power Optimization of Future transistors and a resulting global comparison standard", IEDM 2004.
Shekar Borkar, "Digital Design for Low-Power Systems", IEDM Short Course 2005.
Scott Crowder, "Low Power CMOS Process Technology", IEDM Short Course, 2005.
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