EE282H Programming Assignment #1

K. Olukotun                                                         Handout #
Fall 97/98                                                          EE282H

EE282H Programming Assignment #1

MIPS-Lite Verilog Model
Due: Thursday, October 16, 1997

1.0 Overview

The purpose of this assignment is to familiarize you with Verilog, the MIPS-Lite instruction set architecture, and the MIPS-Lite model. You will be given several test programs and a Verilog model of a MIPS-Lite processor, into which several bugs have been introduced. There are two parts to this assignment.

1.1 Fix the model

The first part of the assignment is to fix the bugs (there are less than 10) in the Verilog model so that the test programs run correctly.

1.2 Fix instruction latencies

The second part of the assignment is to modify the Verilog model so that instructions execute only the stages that they require:

Branch and jump instructions should complete in 3 cycles
ALU, store and jump&link instructions should complete in 4 cycles.

In general, since nop's can be implemented in a variety of ways on real machines. you should not explicitly check for nop's and instead treat them as normal instructions. For example, a nop is typically represented in MIPS-Lite as sll r0, r0, 0. You should treat this as an ALU instruction which completes in 4 cycles. Do not remove the writeback stage for writes to r0.

Make sure to check the the class web page regularly for extra information. The assignment is to be done in groups of two people. If you have trouble getting the Verilog simulator to work, please see one of the TAs.

2.0 What to turn in

Rather than physically hand in a hardcopy of your modified Verilog model, you will be asked to electronically submit your code and a README file. The README file should contain:

a brief description of bug fixes
modifications that you made to the Verilog model (e.g. new modules)

Exact details on how to electronically submit is discussed at the end of this document.

3.0 Details

3.1 Setup

Before doing anything else, add the following to your .login file:

source /usr/class/ee282h/setup

The files needed for this programming assignment are located in /usr/class/ee282h/p1. In this directory there are two subdirectories:

testcode - contains sample test programs
verilog - contains the MIPS-Lite verilog model

Create your own directory and copy all of the files and the directory structure into it by typing:

cp -r /usr/class/ee282h/p1 <your directory>

3.2 Compiling Test Programs

In order to compile test programs, login to one of the SGI machines in Sweet Hall (raptor, firebird, or junior machines). These stations use MIPS ISA (sort of like the MIPS-Lite) processor and will generate the correct object code for our verilog model. Do not try to compile test programs on one of the Sun SPARC workstations, it wont work! Since people taking graphics courses have priority, please use these SGI machines remotely. You can type hinv on an SGI machine to confirm that you are using a MIPS processor.

Once you are logged onto one of the SGI stations, go to the testcode directory. In the testcode directory there are several sample test programs as well as two scripts which compile the test programs for you.

3.2.1 Compiling C test programs

To compile a C program such as bubble.c type the following from the testcode directory:

compile282h bubble.c

Ignore any "nop required" error messages you get from the C compiler. Make sure you must run this program on a MIPS machine. The cc282h script will generate the following files:

bubble.s - the MIPS assembly code produced by the compiler
bubble.dis - the disassembled object code produced by the assembler
bubble.data - the user program data_segment used by the verilog model
bubble.text - the user program text_segment used by the verilog model

The bubble.text and bubble.data files are automatically copied into the verilog directory. When writing a C program, make sure that the main() procedure is the first procedure in the file in order to ensure that it will be first one that the MIPS-Lite simulator will encounter in the text segment.

3.2.2 Compiling MIPS assembly test programs

To compile a MIPS assembly program like add.s, type the following from the testcode directory:

compile282h add.s

Again, you must run this program on an MIPS machine. As with the C program compilation, the compile282h script will generate the following files:

add.dis - the disassembled object code produced by the assembler
add.data - the user program data_segment used by the Verilog model
add.text - the user program text_segment used by the Verilog model

Remember to put a jr r31 instruction at the end of your assembly program so that the simulation will terminate correctly. When in doubt, follow the examples provided in the testcode directory.

3.3 Running the Verilog MIPS-Light model

Verilog is licensed to run only on the Sun SPARC stations in Sweet Hall (elaine, saga and epic machines). Since someone else will often be sitting in front of the machines running Verilog, you may have to run Verilog remotely. To do this type

	xhost +

on your current machine, then rlogin to a Sun SPARC machine that runs Verilog and in the terminal window type:

	setenv DISPLAY :0.0

To run the Verilog model, change to the verilog directory and type

	verilog -f master

This will compile all of the verilog source files for the MIPS-Light model. There are also three command line arguments which allow you to use other verilog features:

+waves - use the graphical waves display
+regs - use the graphical register display
+output - dump the final contents of memory to a file called memory.core

You can use any combination of these options. Try using all three!

	verilog -f master +waves +regs +output

Once Verilog has started up, type . [return] and you will run the most recently compiled program. By clicking on the buttons of the graphical register display, it is possible to step through the execution of the program. You can see what is happening during every cycle and look at the values in all the registers. To exit Verilog, type [Ctrl-D].