FLASH MEMORY
Description
The recipes must be kept in some sort of static storage. This way they will remain during
power cycles and can be recalled at any time. Flash media was chosen because of it's small
size and large density. Atmel's DataFlash was chosen in particular because of its simple
SPI interface. The current prototype uses a AT45DB021B 2 Mbit flash to store data.
Circuit
The DataFlash currently available from Atmel runs at 2.7 V. However the rest of the board
runs at 5 V. Luckily the AT45DB021B can accept input voltages up to 6.25 V. Therefore SPI
outputs from the AVR (SCK, MOSI, and SS) are connected to the inputs of the DataFlash through
simple 330-ohm resistors.
Going the other way (from the slave output of the DataFlash to the master input of the AVR)
is not as simple. Eventually (see the Difficulties section on the Schematic page) the
voltage of the DataFlash was raised to 3.5v. This allowed the same simple resistor
connection. A 220-ohm resistor was used because it was handy. I don't believe the value is
critical.
Driver
Before using SPI it's control register, SCPR must be set up properly. I chose to disable
interrupts, enable SPI (of course!), send the MSB first (in accordance with the DataFlash
data sheet), make the AVR a master, make SCK high when idle, set the clock phase bit to 0,
and run SPI at 1/4 the clock frequency. The choice of clock polarity and clock phase were
made after consulting the AVR 335 application note. This corresponds to SPI mode 3.
After that, the AVR does most of the work since SPI is built in. I wrote a simple function called
MasterOut() which appropriately sets the SS line, writes the master's output to the SPI data
register, and waits for the transfer to complete (indicated by the SPIF flag in the SPI status
register). The MasterOut() function also returns whatever was written into the SPI data
register by the slave DataFlash device, although this information is not always relevant.
Before sending commands to the DataFlash the status bit must be checked. If bit 7 of the
Status register is 1 then the device is ready. The status is checked by sending a Read status
command and then shifting out a don't care byte. The byte shifted in is the status byte.
However, I did not find this sufficient. I found that only by adding explicit delays before
commands are sent would the device function properly and reliably.
The way it is designed the Digital Cookbook will always be writing an entire screen buffer.
The screen buffer is transferred to one of the 2 internal buffers of the DataFlash. This is
done by sending a command to select a buffer (buffer 1 is always used) followed by 15 don't
care bits (0's are used) and a 9 bit address to start writing within the buffer. The first
bit is always 0 and the next 8 bits correspond to the address within the screen buffer.
Finally the data for that address is sent. This is repeated for every byte of the screen buffer.
After all bytes are transferred between buffers a command and the destination page are sent to
transfer the DataFlash buffer to DataFlash main memory. The built-in erase feature is used.
Reading from the DataFlash is done directly from main memory. The status bit must be
checked first, similar to writing. The read command is sent follwed by the address of the
page to retrieve, the address within the page (always 0), and 32 don't care bits (0's are used). After
that each byte shifted out brings in the next byte from the DataFlash. The bytes are then
stored in the screen buffer.
File System
The 2M-bit DataFlash chip that is used in this project is stored in pages of 264 bytes. Some sort of
file system is necessary to map recipe and menu files to memory pages. The current file system maps
each screenful of information to a page of memory since the screen contains 21 x 12 = 252 bytes and
that is close to 264. In the current protoype version there is only one menu screen and it resides
in memory at page 0. After that each recipe is allotted 4 pages. This is not meant to be an ideal or
optimal solution at this time, but instead an easy one that will readily show the basic capabilities
of the system as a whole.