1/16 - Preliminary Project Proposal

This is the initial design specification for your chip. It should be short, just long enough to give us a feeling for what you are going to build, the internal organization, and the external interface (including the number of pins, etc).

1/30 - Detailed Project Report

This is a more detailed description of the chip that should contain a description of all the cells and how they work. You should have a running functional model of the chip by this time (at least it should be very close to working). You should also have started generating SUE schematics for each of the cells.

2/6 - Verilog Complete

This is not a report, but rather a time when the Verilog description of the chip should be completed and verified. You should also have finished the schematics for the cells and have started putting them together as you simulate and verify each cell and circuit block.

2/20 - Cell Layout Completion

Crunch time - all the cell layout should be finished by now. The chip should be almost complete, with only some wiring left. Simulation of the cells and some of the blocks should be done.

2/27 - Layout Completion

Everything should be put together. The next week should be occupied with top-level LVS and DRC and full-chip simulation.

3/7 - Ship for Fabrication

The chip layout should be completely simulated and ready to be shipped for fabrication. Only chips that pass the simulation tests will be submitted for fabrication.

3/13 - Final Project Report

This is the final report for your project. It should include a table of the time spent in the class, as well as suggestions for improvement. More details will be handed out later.