EE272
HO#
Name
1
Class information
2
Student information
3
Preliminary project proposal
4
Project ideas
5
Lecture 1: Class overview
6
Lecture 2: Machine Design
7
Lecture 3: Verilog
8
Lecture 4: Verilog Debugging
9
Detailed Project Proposal
10
Lecture 5: Magic
11
Lecture 6: IRSIM and Gemini
12
Lecture 7: Synthesis and Place and Route
13
Lecture 8: Tapeout Checks
14
Lecture 9: Pads
15
Lecture 10: Analog layout
16
Final report



Assignments


Page modified by Ken Mai; Last Updated recently
Page created by Jeshuah Sniderman.