Synopsys/Lager Frequently Asked Questions

Helpful Documents

• Lager Homepage

Questions

A: Make sure that you are sourcing all of the correct files and have everything setup correctly. You need to be sourcing /usr/class/ee272/csh. Also, you need to have the symbolic links for synopsys and lager as stated in the synopsys/lager handout (link here someday).

In the handout, it says to make a link ~/.synopsys.setup. Copy the same link to ~/.synopsys.

Note that there are various errors caused by not having the LD_LIBRARY_PATH environment variable set for some tools. Unfortunately if you do have this set, a lot of other stuff breaks. We get around this by putting little shell script wrappers on some of the tools (verilog, navver, DMoct).

Do not use implied latches in your verilog. It will not get synthesized well, and could cause the synthesized logic to fail.

Q: The tool v2sdl gives me a parsing error on one of the lines of my controller.mapped. What is causing this?

A: Among other things, it is possible that you have a feedthrough or an output that is always 0 or 1. Look at the line in question in controller.mapped. See if one of the inputs to the standard cell is 0 or 1 always. If so, go back and fix your verilog code, and re-run synopsys/lager.

Q: My synthesized logic block is way too big. How can I make it smaller?

A: A former 272 student prepared a document on how he got his controller to shrink by a factor of 2 (from ~400 cells to ~200 cells). It is available in 3 formats:

• troff (original)
• Plain text
• Postscript

Q: The module that I want to synthesize has hierarchy. How can I get Synopsys to synthesize it as a single entity?

A: To flatten hierarchy in synopsys, after you read in the verilog file, push down into the top module. Select all of the sub-modules. Then from the Edit menu, choose the Ungroup menu item. You should then see synopsys expand out all of the sub-modules.

Q: How can I specify which side the synthesized logic inputs and outputs appear on in the layout?

A: At the end of the .sdl file there are a bunch of lines that have in them "(TERM_EDGE ??)". Replace the ?? with either TOP, BOTTOM, LEFT, or RIGHT to specify the edge. Don't forget to uncomment the line (remove the ";" at the beginning of the line.

Q: How can I specify the ordering of the inputs and outputs of the synthesized logic?

A: After the TERM_EDGE specifier, you can add a similar specifier for TERM_RELATIVE_POSITION. The relative position is a number between 0 and 1 inclusive. If you put in -1.0 this indicates that you want a random ordering.

Please see the manual pages for sdl and for Stdcell for more info. Remember that you need to use the command "lagerman" to access those manual pages. For terminals on the RIGHT and LEFT a high number corresponds to being closer to the top. For TOP and BOTTOM a high number corresponds to being rightmost.

A fragment of a .sdl file with the sides and ordering set would look like:

(terminal RegWrite_s1 (TERM_EDGE TOP)(TERM_RELATIVE_POSITION 0.0))
(terminal RegNum_b_s1[0] (TERM_EDGE TOP)(TERM_RELATIVE_POSITION 0.1))
(terminal RegNum_b_s1[1] (TERM_EDGE TOP)(TERM_RELATIVE_POSITION 0.2))
(terminal RegNum_b_s1[2] (TERM_EDGE TOP)(TERM_RELATIVE_POSITION 0.3))
(terminal Opcode_s1[0] (TERM_EDGE TOP)(TERM_RELATIVE_POSITION 0.4))
(terminal Opcode_s1[1] (TERM_EDGE TOP)(TERM_RELATIVE_POSITION 0.5))
(terminal Opcode_s1[2] (TERM_EDGE RIGHT)(TERM_RELATIVE_POSITION 0.0))
(terminal Opcode_s1[3] (TERM_EDGE RIGHT)(TERM_RELATIVE_POSITION 0.1))
(terminal Opcode_s1[4] (TERM_EDGE RIGHT)(TERM_RELATIVE_POSITION 0.2))
(terminal Opcode_s1[5] (TERM_EDGE RIGHT)(TERM_RELATIVE_POSITION 0.3))
(terminal BusDrvExt_s1 (TERM_EDGE RIGHT)(TERM_RELATIVE_POSITION 0.4))

Here are some random synopsys/lager hints:

• In /usr/class/ee272/stdlib/ there is a verilog file std272.v. It contains verilog descriptions of all of the standard cells. Using this and your .mapped file from synopsys, you can replace whatever module(s) you synthesized in your verilog model. Thus, you can check to see if the synopsys output will work in your machine.
• Avoid feedthroughs in the things that you synthesize. The feedthrough standard cell is behaving strangely, and may not give you the desired result. You can tell if you have any feedthroughs by looking at the .sdl file. At the beginning of the file, there is a list of all the cells that are used. Make sure that none of them are "feed".
• To flatten hierarchy in synopsys, push down into the top module, after you read in the verilog file. Select all of the sub-modules. Then from the Edit menu, choose the Ungroup menu item. You should then see synopsys expand out all of the sub-modules.
• Avoid constants in the things that you synthesize. If it turns out that one of your outputs is always high, then take it out of the module.
• If you want to be sure that your layout is drc error free, you can use the command :drc check to drc check everything under the box.
• After you are done synthesizing, look over the layout. Sometimes the tools will mess up. Please let us know if you encounter problems with the tools.