*******************************************
* Using Verilog to generate Irsim Vectors *
*******************************************

You can use Verilog to generate Irsim vectors if:

1. You can make your Verilog do what you want your circuit to do
2. The nets you want to stimulate and verify exist in your Verilog module
3. Some node in your Verilog specifies the direction of each bidirectional
	node to stimulate/verify

Things will be easier if:

1. Your outputs and bidirectional ports have "v" or "s" timing types
2. The Verilog names for those ports end with underbar-timingtime-phase
	(like foo_v2)
3. Irsim names for buses end in bracketed numbers just as thier Verilog
	counterparts (bus_s1[0], bus_s1[1], bus_s1[2], etc.)

The steps are:

1. Create a "snooper" module
2. Instantiate the snooper in your Verilog
3. Run the Verilog as usual (remember to use the -x flag)
4. Quit Verilog
5. Fire up Irsim
6. Run "versim.cmd", which your Verilog run generated
7. Look for messages from Irsim, "Assert Failed" - no news is good news


*****************************
* Creating a Snooper Module *
*****************************

A snooper module has all of the relavent nodes of your Verilog model as inputs.
It works by calling PLI functions like "$rsim_log_input" and "$rsim_log_output"
whenever the appropriate signals change or need to be checked in Verilog. The
PLI functions create the file "versim.cmd".

There's a program called snoopgen in the class directory. It will 
automatically generate the snooper.v module for you. All it needs is
an input file that lists the nodes you want to snoop and whether
they are inputs, outputs, or input/outputs.

Here is an example of its input file:

i Phi1
i Phi2 phi2
c Phi1
c Phi2
i input
i inbus[3:0] inbus
o outbus_s1[7:0]
o output_v2
b control_node i bibus_v1[3:0] irsimbibus
b control_node o biput_s2

Each line specifies either a clock, an input, an output, or a
bidirectional port. Clock names and timing-type suffixes are used to
match phases. "i", "o", and "b" lines include an optional irsim name,
which can be different from the Verilog name. 

Clocks will usually also be inputs.

For vectors, only put the range on the Verilog name.

The "i" or "o" in a "b" line specifies the sense of the control node.
If "i" is specified, the biput is an input when the control node is
high.

If clocks or biput-controlling nodes are also inputs or outputs, list
the inputs or outputs earlier than the "c" and "b" lines in the input
file.

You will probably be able to take a snooper module directly from
snoopgen. If not, running snoopgen will still illustrate the form of
snooper modules.

A typical use of snoopgen from the UNIX command like would look like:

	snoopgen system.in > snooper.v

Note that snoopgen does not automatically make an output file. You have to
explicity dump the output to a file. The file "system.in" would be a
snoopgen input file.


*********************************************
* Instantiating the Snooper in your Verilog *
*********************************************

It can go wherever you want, but it may have to be within the module
you're checking or the next one above to have easy access to the nodes
it needs. You may have to access some nodes through the hierarchy -
e.g., padframe.pad11.ENABLE


***********************
* Running the Verilog *
***********************

Use rsimverilog instead of verilog. Using "verilog -x" will do the
same thing as "rsimverilog".

You may want to run the Verilog for a fixed period of time, by firing
it up in interactive mode (-s on the command line) and running something like:

C1> #1000 $stop;
C2> .


*****************
* Running Irsim *
*****************

Running Irsim will be as simple as typing "versim", but you may first
want to set up analyzers, checking power and ground for fragments,
etc.

It should not be necessary to use the irsim "clock" command.


*********
* NOTES *
*********

2/15/96 - demon@leland

At least the /usr/class/ee/bin/systems/sun4c_411/snoopgen binary has a
little bug. If there are multiple blank lines after the last node
specification, snoopgen will replicate the last node listing that many
times. In writing your input file just hit return once after the
last line. Also this binary seems to have been compiled from older
source code that does not handle qualified signals. 

A newer version of the binary can be found in /usr/class/ee272/bin/. 
The source code for this newer version is in /usr/class/ee272/src/snoopgen/.
This version handles qualified signals and skips over any blank lines
in the input file. The older version would repeat the last entry
for any blank line that appeared.