/****************************************************************************** * This information is confidential and proprietary and may not be disclosed * * to any third party, in any manner, without prior written permission from * * Systems Science Inc. Receipt of this material shall be considered * * acceptance of the conditions specified herein. * * * * This file contains a Verilog model for demonstrating Systems Science's * * Magellan software. * ******************************************************************************/ module top; /************************************************************************* * This module instantiates a four bit adder and a four bit * register. The adder and register are connected together by a four bit bus. * This module also provides the stimulus for the adder and coordinates the * transfer of the adder's output to the register. *************************************************************************/ parameter BREAKTIME=120; parameter LASTTIME=250000; parameter ADDENDLIM=15; reg [3:0] add1, add2; // two four bit quantities to be added reg enAdd; // 0 = noop, 1 = ENABLE adder to drive bus wire enReg; // 0 = noop, 1 = ENABLE register to drive bus reg loadReg; // 0 = noop, 1 = LOAD register from bus wire [3:0] dataReg; // value stored in 4bit register wire [3:0] bus; // bus driven by output of 4bit adder and 4bit register // This block demonstrates the Magellan system tasks initial begin // next line enables interface to Magellan DURING simulation $ssi_navigator; $stop; // next line records all variables for display in SimWave DURING simulation $ssi_navrecord; // next line creates database file for connectivity info AFTER simulation // $ssi_navdbase( "nav.dbase", "adder.v" ); // next line records all value changes for debugging AFTER simulation // (changes stored in a VCD file, an ASCII dump of simulation results) // $dumpvars; // next 3 lines save the last 1 megabyte of value changes // for debugging AFTER the simulation ( changes stored in circ.dump ) // $ssi_navconfigure( "-dumpsize 1" ); // $ssi_navconfigure( "-dumpname circ.dump" ); // $ssi_navdump; end // generate all 256 different combinations of add1 and add2 initial begin enAdd = 0; loadReg = 0; for( add1 = 0; add1 < ADDENDLIM; add1 = add1 + 1 ) begin for( add2 = 0; add2 < 15; add2 = add2 + 1 ) begin #20 enAdd = 1; // enable adder to drive bus #10 loadReg = 1; // load adder results into register #10 loadReg = 0; // reset load line #10 enAdd = 0; // disable adder output, enable register end end end // stop every BREAKTIME ticks always begin #BREAKTIME if( $time >= LASTTIME ) $finish; $stop; end // instantiate the four bit adder fourAdd fourAdd(add1, add2, enAdd, bus); // instantiate the four bit register fourReg fourReg(bus, dataReg, loadReg, enReg); // generate a non-overlapping pulse to enable the register output pulse pulse( enReg, enAdd ); endmodule module fourAdd(add1, add2, enable, sum); /*************************************************************************/ /* */ /* This module implements a four bit ripple carry adder. */ /* */ /*************************************************************************/ input [3:0] add1, add2; // two four bit quantities to be operated on input enable; // enable output output[3:0] sum; // sum or difference of add1 and add2, output wire sum0, sum1, sum2, sum3; // intermediate sum signal wire carry0, carry1, carry2; // intermediate carry signal wire carryIn = 'b0; // hardwire carry in signal // Instantiate the four required full adders fullAdder fadd0(add1[0], add2[0], carryIn, carry0, sum0); fullAdder fadd1(add1[1], add2[1], carry0, carry1, sum1); fullAdder fadd2(add1[2], add2[2], carry1, carry2, sum2); fullAdder fadd3(add1[3], add2[3], carry2, carryOut, sum3); // Gate the output of the adder onto the bus bufif1 u3( sum[3], sum3, enable ); bufif1 u2( sum[2], sum2, enable ); bufif1 u1( sum[1], sum1, enable ); bufif1 u0( sum[0], sum0, enable ); endmodule module fullAdder(a, b, ci, co, s); /*************************************************************************/ /* */ /* This module implements a one bit fullAdder. */ /* Completely gate level. */ /* */ /*************************************************************************/ input a, b, ci; output co, s; xor a_b_c_xor( s, a, b, ci ); and a_and_b( a_b_o, a, b ); and a_and_ci( a_ci_o, a, ci ); and b_and_ci( b_ci_o, b, ci ); or co_or( co, a_b_o, a_ci_o, b_ci_o ); endmodule module fourReg(data, peek, load, enable); /*************************************************************************/ /* */ /* This module implements a four bit register. */ /* Register is loaded with "data" on positive edge of clock. */ /* "peek" allows the instantiating module to peek at the contents */ /* "enable" controls when register contents are driven on "data" */ /* */ /*************************************************************************/ inout [3:0] data; output [3:0] peek; input load; input enable; dff( peek[3], load, data[3] ); dff( peek[2], load, data[2] ); dff( peek[1], load, data[1] ); dff( peek[0], load, data[0] ); // Gate the output of the flip flops onto the bus bufif1 u3( data[3], peek[3], enable ); bufif1 u2( data[2], peek[2], enable ); bufif1 u1( data[1], peek[1], enable ); bufif1 u0( data[0], peek[0], enable ); endmodule primitive dff( q, clk, d ); /*************************************************************************/ /* */ /* This is user defined primitive for a D flip-flop */ /* */ /*************************************************************************/ input clk, d; output q; reg q; table r 0 : ? : 0 ; r 1 : ? : 1 ; f ? : ? : - ; ? * : ? : - ; endtable endprimitive module pulse( out, in ); /*************************************************************************/ /* */ /* This module generates a non-overlapping pulse from "in" */ /*************************************************************************/ input in; output out; not #6 n0(inv_in, in); buf #8 b0(del_in, in); and #6 a0(out, inv_in, del_in); endmodule