For students with research and applications interest in VLSI systems.
Working in teams of two, students complete modest-sized digital CMOS chip of
their own design.
The project includes writing a functional model (in Verilog), using
synthesis tools, custom layout, and simulation. Overview
of the issues involved in VLSI design. Topics: design tools
and techniques, complexity management, clocking issues, layout and
floorplanning, design of large array structures, testing and testability
issues. Prerequisites: 271, experience with digital design.
EE272A - 4 units, Win (Mai,Alon,Labonte) TTh 1:15-2:30
The course cannot be taken by SITN students. (Not broadcasted through
SITN.)
