// Define our test module
module test_master_control;

// Define our clock
reg clk, reset, enable;

// Define our other inputs
reg button;

// Define our output from the master_control
wire go;
			
// Instantiate our master_control FSM.
master_control mc(.clk(clk), .en(enable), .r(reset), .button(button), .go(go)); 

// Now set up a clock generator for the simulation.
// This simply starts at the begining (initial) sets the clock to 0,
//  then waits 10 simulation steps #10 and then repeates forever
//  waiting 10 simultion steps and inverting the clock. Note that this
//  is NOT synthesizable. This is PURELY a directive to the simulator
//  telling it what to do. Initial blocks will NOT work in your projects;
//  they are ONLY for simulation!
initial 
	begin
	   clk = 0;
	   #10 forever #10 clk = !clk;
	end

// Now set up some test values for our simulation
initial
	begin
		enable = 0;
		button = 0;
		// Rest our FSM at first, followed by 20 steps of reset high
		// and 20 steps of reset low before we begin.
		reset = 0;
		#20 reset = 1;
		#20 reset = 0;
		enable = 1;
		// Now let's try pulsing the button. Remember that the clock is
		//  20 steps long, so we need to have our pulses be 20 long
		#60 button = 0;
		#60 button = 1;
		#60 button = 0;
		#60 button = 1;
		#20 button = 0;
		#20 button = 1;
		#20 button = 0;
		#20 button = 1;
		#20 button = 0;
		// And let's stop a bit later.
		#1000 $stop;
	end

// Let's print out some key values along the way
initial
	begin
		$monitor($stime,, reset,, enable,, button,, clk,, go);
	end

endmodule