// Module color_control. 
// Requires two pulses of on with no off pulses in between to enable
//  the output out and any pulse of off will disable it. Has a reset
//  and an enable.
module color_control(
					clk,
					en,
					r,
					on,
					off,
					out
					);

// *** INPUTS ***
input clk, en, r;
input on, off;


// *** OUTPUTS ***
output out;
// QUESTION 1: Why is this a register?
// ANSWER 1:
reg out;


// *** WIRES ***
// QUESTION 2: Why is this a wire?
// ANSWER 2:
wire [2:0] current_state_q;
// QUESTION 3: Why is this a register?
// ANSWER 3:
reg [2:0] next_state_d;


// *** STATE DEFINITIONS ***
// QUESTION 4: What kind of state machine is this with this encoding?
// ANSWER 4:
`define WAIT1 3'b001
`define WAIT2 3'b010
`define TURNON 3'b100


// *** NEXT STATE COMBINATIONAL LOGIC ***
// QUESTION 5a, b, c: Why specifically do each of these have to be in the 
//  sensitivity list?
// ANSWER 5a (current_state_q):
// ANSWER 5b (on):
// ANSWER 5c (off):
always @(current_state_q or on or off)
begin
	case(current_state_q)
		`WAIT1: begin
			out = 1'b0;
			// Insert your next-state logic here for state WAIT1
		end
		`WAIT2: begin
			out = 1'b0;
			// Insert your next-state logic here for WAIT2
		end
		`TURNON: begin
			out = 1'b1;
			// Insert your next-state logic here for TURNON
		end
		default: begin
			// QUESTION 6: What happens if this is blank? Try it.
			// ANSWER 6:
			// Insert something reasonable here. 
		end
	endcase
end


// *** STATE FFs ***
dffre #(3) state_ff(.clk(clk), .en(en), .r(r),
				.d(next_state_d), .q(current_state_q)
				);

endmodule