///////////////////////////////////////////////////////////////
// control.v
// Created by Paul Hartke (phartke@stanford.edu) Apr 22, 2002 
// Modified by 
//
// FSM statemachine for the EE183 Verilog tutorial.
// Accepts a single input pulse that advances the state machine
// The three outputs are mealy outputs that load the elements
// in the tutorial datapath
//
///////////////////////////////////////////////////////////////
module control (pulse, load_a, load_b, load_c, 
  clk, reset, enable);
	
  input clk;
  input reset;
  input enable;
 
  input pulse;
  output load_a, load_b, load_c;  // Mealy Outputs
  
  // local variable declarations
  reg load_a, load_b, load_c;

  // State Machine Declarations...
  `define FSM_NUM_DFF 2
  `define STATE0 2'b00
  `define STATE1 2'b01
  `define STATE2 2'b10
  `define STATE3 2'b11
  reg [`FSM_NUM_DFF-1:0] next_state_d;
  wire [`FSM_NUM_DFF-1:0] state_q;
  
  // Next state logic...
  always @(pulse or state_q)
    begin
      if (pulse == 1'b0)
        case (state_q)
          `STATE0 : begin 
          	next_state_d = `STATE0;
          	load_a = 1'b1;
          	load_b = 1'b0;
          	load_c = 1'b0;
          	end
          `STATE1 : begin
          	next_state_d = `STATE1;
          	load_a = 1'b0;
          	load_b = 1'b1;
          	load_c = 1'b0;
          	end
          `STATE2 : begin
          	next_state_d = `STATE2;
          	load_a = 1'b0;
          	load_b = 1'b0;
          	load_c = 1'b1;
          	end
          `STATE3 : begin
          	next_state_d = `STATE0;
          	load_a = 1'b0;
          	load_b = 1'b0;
          	load_c = 1'b0;
          	end
          default : begin
          	next_state_d = `STATE0;
          	load_a = 1'b0;
          	load_b = 1'b0;
          	load_c = 1'b0;
          	end
        endcase     
      else // (pulse == 1'b1)
        case (state_q)
          `STATE0 : begin 
          	next_state_d = `STATE1;
          	load_a = 1'b1;
          	load_b = 1'b0;
          	load_c = 1'b0;
          	end
          `STATE1 : begin
          	next_state_d = `STATE2;
          	load_a = 1'b0;
          	load_b = 1'b1;
          	load_c = 1'b0;
          	end
          `STATE2 : begin
          	next_state_d = `STATE0;
          	load_a = 1'b0;
          	load_b = 1'b0;
          	load_c = 1'b1;
          	end
          `STATE3 : begin
          	next_state_d = `STATE0;
          	load_a = 1'b0;
          	load_b = 1'b0;
          	load_c = 1'b0;
          	end
          default : begin
          	next_state_d = `STATE0;
          	load_a = 1'b0;
          	load_b = 1'b0;
          	load_c = 1'b0;
          	end
        endcase 
    end 
  
  // State Elements...
  dffre #(`FSM_NUM_DFF) state_reg (.d(next_state_d), .q(state_q),
    .clk(clk), .r(reset), .en(enable));
  
endmodule