Xilinx BRAM Usage Instructions

If you have any questions, email phartke@stanford.edu

The Xilinx Spartan2 FPGA used in Lab contains 10 4-Kilobit Block Rams (BRAMS) that are a very useful resource. They are dual-ported, which means they have two totally independent access ports (however, you can even read and write to the same location and the BRAM will provide either the old or newly written data). In addition, they are synchronous, which means the outputs are registered. To use the BRAM as a ROM, the default initialization values can be specified.

Xilinx FPGAs also provide "distributed memory" which creates larger memory blocks out of the flip-flops in the fabric. This memory is not very dense and should only be used for small memories or when the BRAMs are exhausted.

CoreGen (Core Generator) is the Xilinx wizard that creates various memory sizes and set other properties from the underlying BRAM primitives. coregen can create all sorts of other cores--in general you should design all the logic for the project using the methods covered over the course. However, certain blocks--such as multipliers--are appropriate to use Coregen for. Ask one of the teaching staff before using any other Coregen modules besides memory.

In order to simulate the Xilinx BRAMs in Modelsim, ModelSim must be made aware of the Xilinx CoreGen simulation models. Xilinx Solution Record #8066 contains a script to do this for us. Make sure to use the ModelSim SE instructions. This needs to be done once for each ModelSim install. Unzip the ftp://ftp.xilinx.com/pub/swhelp/mti/xilinx_lib_4.zip onto the harddrive and execute "source c:/xilinx_lib_4.tcl" in Modelsim. Here are the options to select:

Creating BRAM memories with CoreGen

Launch CoreGen from within Xilinx (Tools-->Design Entry-->Core Generator...)

Double clicking on a core type to launch a wizard for that core:

Select the following project options with the "Project-->Project Options" menu:

After you select the appropriate options, press "Generate" to create the core. The Coregen Memory Editor under Tools-->Memory Editor can be used as the initialization file for the memory creating a ROM. While the memory editor is fun, you'll probably want to write your own .COE files.
That's really all there is to it.

Xilinx Implementation
Coregen will deposit a *.v file with the same name as the coregen element (in this case paul_bram.v) into the project directory. Add this source file to the project. Synthesize and implement as normal. It actually worked :-)

Simulation Method

Line 72 loads the CoreGen library file that was created above
Line 73 compiles the three verilog source files (note that paul_bram.v was generated by coregen)
Line 74 loads the modules into the simulator
Line 75 runs the modules
Note that the output changes one cycle after the address since the memory is synchronous.

The testbench file includes the line "`timescale 1ns/10ps" that ensures all the simulation delay times are correlated. We are not using that feature and its only there to keep down some warnings in Modelsim.

The source files used for this example are here.

If you have any questions, email phartke@stanford.edu