EE 108: Digital Systems I
Stanford
University, Winter 2002-2003
Announcements
- Final Project Demos Schedule
- Some useful Utilities to take image and sound
files and convert them intto FPGA-friendly formats. See Lecture Notes 15
for more info.
- Project Information is here.
- Xilinx BRAM Usage Instructions are here.
- The Milestone #1 schedule for the Final Project can be found here.
- Please download the updated version of HW3. There was a typo. Mux5 should be Mux8
- The verilog sources presented in class have been posted here
- Xilinx Foundation 4.2 Installation Instructions. We are going to use the
Xilinx Foundation FGPA tool suite this quarter and all the info to get it
installed is here.
- Modelsim Installation Instructions. We are going to use the HDL Simulator
ModelSim this quarter and all the info to get it installed is here.
- Lab Section Assignments are now available.
- Sign yourself up on EEClass.
Grades will be posted on EEClass.
- TA Office Hours are posted below
- Prof Dally's office hours are Monday 3-4 and Thursday 11-12 in Gates
301
- There is a typo in HW1. Q2 should have RP and RN in units
of kOhms*um instead of kOhms/um^2
- Here is the schedule
of the quarter, with reading assignments for each lecture. Except for the
first week, specified sections of the book must be read prior to
corresponding lecture.
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Handouts
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Lab files
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HW files
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General Information
EE 108 is an introduction to digital circuits and their
applications. Topics covered in lecture are explored in weekly laboratory
assignments and a three-week final project. Lecture topics include:
- Digital circuit, logic and
system design
- Digital representation of
information
- MOS logic circuits
- Digital transmission lines
- Combinational logic design
- Logic building blocks,
idioms and structured design
- Sequential logic design and
timing analysis
- Clocks and synchronization
- Finite state machines
- Microcode control
- Digital system design
- Control and datapath
partitioning
The EE 121 lab has seven stations, each with a Pentium III PC, a C.A.D.E.T.
board from E&L Instruments, an HP 54601 digital oscilliscope, an HP 3312
function generator.
Students implement their designs during weekly lab sessions, using Xilinx
Foundation 4.2i, simulate using modelsim, and test them on XC2S100 Xilinx
Spartan-II FPGA on XSAv1.0 boards, plugged on an XStendv1.3 board. Labs lead
students to interface with SDRAM, VGA output and audio output.
Lectures
Tuesdays and Thursday, 1:15-2:30, Gates B12
Laboratory
Packard 127. Telephone: 650-725-1748
Required Textbook
Fundamentals of Digital Logic with Verilog Design,
Stephen Brown, Zvonko Vranesic, McGraw Hill
Grading
20% Laboratory Assignments
20% Homework Assignments
40% Midterm examinations (2)
20% Final project
Course Schedule and Reading Assignments
Here is
the worksheet
Chapters of the textbook are to be read prior to the lecture they
correspond to.
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Teaching Staff
Instructor
Bill Dally
Office: Gates room 301
Office hours: T 10-11 and Th 11-12
Email: billd@csl.stanford.edu
Phone: 650-725-8945
Fax: 650-725-6949
Teaching Assistants
Paul Hartke
Office: Packard 127
Office hours: Monday 1:30pm-3:30pm
Email: phartke@stanford.edu
Phone: 650-725-1748
Sam Mazin
Office: Packard 127
Office hours: Sunday 7pm-9pm
Email: smazin@stanford.edu
Phone: 650-725-1748
Frederic Sarrat
Office: Packard 127
Office hours: Monday 7pm-9pm
Email: fsarrat@stanford.edu
Phone: 650-725-1748
Course Administrator
Pamela Elliot
Office: Gates 303
Email: pamela@csl.stanford.edu
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Resources
Tutorials
Documentation
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Last modified: Sat Nov 23
08:31:04 PST 2002