H.-S. Philip Wong
Professor of Electrical Engineering
Education:
B.Sc. Hons. (1982) University of Hong Kong, M.S. (1983) State University of New York, Stony Brook, and Ph.D. (1988) Lehigh University.
Biography:
Prof. Wong joined Stanford in September, 2004 after 16 years at IBM Research, T.J. Watson Research Center, Yorktown Heights, New York. While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM’s strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.
His research interests are in nanoscale science and technology, semiconductor technology, solid state devices, and electronic imaging. He is interested in exploring new materials, novel fabrication techniques, and novel device concepts for future nanoelectronic systems. Novel devices often enable new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven.
He is a Fellow of the IEEE and served on the IEEE Electron Devices Society (EDS) as elected AdCom member from 2001 – 2006. He served on the IEDM committee from 1998 to 2007 and was the Technical Program Chair in 2006 and General Chair in 2007. He served on the ISSCC program committee from 1998 – 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. Currently, He serves on the Executive Committee of the Symposia of VLSI Technology and Circuits. He was the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 – 2006. He is a Distinguished Lecturer of the IEEE Electron Devices Society and also a Distinguished Lecturer of the IEEE Solid State Circuits Society. He has taught several short courses at the IEDM, ISSCC, Symp. VLSI Technology, SOI conference, and SPIE conferences. He is a member of the Emerging Research Devices Working Group of the International Technology Roadmap for Semiconductors (ITRS).
RESEARCH GROUP: Nanoelectronics and Nanotechnology
(click here for group webpage)
Keywords: Nanotechnology, nanoelectronics, solid-state devices, Si CMOS, solid-state imaging.
School of Engineering Annual Report (2006-2007) – Click on Profiles
CURRENT PROJECTS:
Nanoscale CMOS Device
Physics and Device Design (FCRP
MSD, FCRP C2S2, NSF, Stanford
INMP, Industry funding)
Currently, we are working on two topics: (1) III-V compound semiconductor as a channel material for high-performance CMOS, and (2) circuit-level performance modeling and optimization for end-of-the-roadmap CMOS devices. Transport-enhanced channel materials will improve FET device performance. We are developing contact technologies for III-V FETs. The experimental work is coupled with modeling to enable optimization of the contact design. We also develop compact modeling tools for III-V FET circuit design and performance benchmarking. As devices scale to small dimensions, parasitic capacitances and parasitic resistances play an increasingly important role in circuit/system level performance. We develop accurate parasitic capacitance and parasitic resistance models to enable circuit/device optimization and to explore new device design options.
Nanoelectronic Devices (FCRP C2S2, FCRP IFC, FCRP FENA, NSF,
DARPA)
Logic devices beyond the silicon CMOS device scaling roadmap. Project scope covers new device concepts, device physics, circuit design, modeling, and device fabrication using novel nanoelectronic materials such as carbon nanotube and semiconductor nanowires as well as novel concepts such as nanoelectromechanical (NEM) relays.
We continue to develop and enhance our carbon nanotube transistor compact device model for circuit simulation. We are working on robust circuit design and fabrication for carbon nanotube electronics including active devices and interconnects (wiring). Imperfections in carbon nanotube material synthesis are being analyzed and ways to mitigate the imperfections are investigated both theoretically and experimentally. We develop synthesis techniques to achieve high-density, aligned growth of carbon nanotubes as well as low temperature carbon nanotube growth for electronics applications. Both digital logic and high-frequency analog applications are explored.
Nanoelectromechanical (NEM) relay represents a departure from the conventional transistors and offers unique advantages such as zero off-state leakage and energy-reversible operation for low standby power and low dynamic power. We work on experimental fabrication of NEM relay and circuits as well as the development of modeling tools for device design and circuit design.
Novel Memory and
Storage Devices (CIS Seed Funding, SRC, Stanford
NMTRI, Industry funding, LBNL Molecular
Foundry)
Memory and storage devices beyond the technology roadmap. The projects scope covers new device concepts, device physics, modeling, and device fabrication. At present, we work in three areas: (1) memory cell selection device, (2) phase change memory, and (3) metal oxide memory. The main topics include (a) nanowire pn-junction diode and other novel memory cell selection device, (b) device physics and scaling trend of phase change memory and metal oxide memory, (c) synthesis and properties of phase change nanoparticles, and (d) new phase change memory cell structure design that can provide high reliability, low power consumption, and possibly multi-bit operation. Memory cell designs are tested with simulation tools using multi-physics simulation tools that incorporate electrical conduction, heat conduction and phase change. We are developing methodologies to measure the thermal properties of small volume phase change materials for better device modeling and device design. We are also exploring new materials for phase change memory.
Nano-bio (DARPA)
We are developing nanoscale electronic devices and circuits
to emulate the functions of synapses and neurons.
Self-Assembly for
Nanoelectronics (SRC, NSF, NRI)
Use of diblock copolymers for the fabrication of nanoelectronic devices. The focus is on device fabrication and process integration. Currently, we are focusing on fabrication of a functional MOSFET using diblock copolymer as a patterning technique for features at the sub-20 nm scale. A long-term (5 year) goal of this project is to fabricate a functional device array (e.g. diodes, FETs, SRAM cells) using self-assembly.
Solar Cells (GCEP, LBNL
Molecular Foundry)
We are developing solar cells based on semiconductor (Si, Ge, III-V) nanowires.
Classes:
EE 21N Freshman Seminar (new class, Autumn, 2006, next offerings: Autumn 2007, Autumn 2008) – “What is Nanotechnology?”
Textbooks: "Engines of Creation: The Coming Era of Nanotechnology" by Eric Drexler (Anchor Books 1986), and "Prey" by Michael Crichton (Harper Collins 2002).
EE 320
(evolved from EE 218, new in 2008/09, Spring 2009, next offerings: Spring,
2010, Spring 2009) “Nanoelectronics” (There is no
required textbook for this course)
(slides for 1st
lecture of EE 218 back in Autumn 2005)
EE 316 (Winter) “Advanced VLSI Devices”
EE 310
(Winter) (with Prof. Krishna Saraswat and Prof.
EE 309 (new class, Spring, 2006, next offering: Autumn, 2007, Autumn 2009) “Semiconductor Memory Devices and Technology” (There is no required textbook for this course) – Prerequisite: EE 216. Preferred: EE 316, EE 313, EE 311
EE 392B (Spring, 2005, not offered in the near future) “Introduction to Image Sensors and Digital Cameras” (with Prof. Abbas El Gamal)
EE 310 Seminar
slides:
October 5, 2004. Download here. (rather old, kept here for historical reasons)
Contacts:
H.-S. Philip Wong
Center for Integrated Systems, CISX 312
Email: hspwong AT stanford.edu
Phone: +1-650-725-0982
Administrative Assistant: Fely Barerra
Email: fely.barerra AT stanford.edu
Phone: +1-650-723-1349
Selected Recent
Conference Publications:
1. N. Patil, A. Lin, E. R. Myers, H.-S. P. Wong, and S. Mitra,
“Integrated Wafer-Scale Growth and Transfer of Directional Carbon Nanotubes and
Misaligned-Carbon-Nanotube-Immune Logic Structures,” Symp. VLSI Technology, paper 21.2, pp. 205 – 206, Honolulu, Hawaii, June 17
– 20, 2008.
2. M. Caldwell,
S. Raoux, D. Milliron, and H.-S. P. Wong,
"Synthesis and Characterization of Germanium Chalcogenide
Nanoparticles," Particles
2008 Conference: Particle Synthesis, Characterization, and
Particle-Based Advanced Materials, 10-13 May 2008, Orlando, Florida.
3. K. Fife, A.
El Gamal, H.-S. P. Wong, “A 3M Pixel
Multi-Aperture Image Sensor with 0.7μm Pixels in 110nm CMOS,”
International Solid State Circuits Conference (ISSCC), pp. 48 – 49, San
Francisco, February 3 – 7, 2008.
4. K. Fife, A.
El Gamal, H.-S. P. Wong, “A 0.5µm
Pixel Frame-Transfer CCD Image Sensor in 110nm CMOS,” IEEE International
Electron Devices Meeting (IEDM), pp. 1003-1006, December 10 – 12, Washington,
D.C., 2007.
5. D. Akinwande,
Y. Nishi, H.-S. P. Wong, “Analytical
Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass,
Carrier Density, and Quantum Capacitance,” IEEE International Electron Devices
Meeting (IEDM), pp. 753 - 756, December 10 – 12, Washington, D.C., 2007.
6. L. Wei, J.
Deng, H.-S. P. Wong, “1-D and
2-D Devices Performance Comparison including Parasitic Gate Capacitance and Screening Effect,” IEEE
International Electron Devices Meeting (IEDM), pp. 741 - 744, December 10 – 12,
Washington, D.C., 2007.
7. K. Akarvardar,
D. Elata, R. Parsa, G. C. Wan, K. Yoo,
J. Provine, P. Peumans, R. T. Howe, H.-S.
P. Wong, “Design Considerations for Complementary Nanoelectromechanical
Logic Gates,” IEEE International Electron Devices Meeting (IEDM), pp. 299 -
302, December 10 – 12, Washington, D.C., 2007.
8. G.F. Close, H.-S. P. Wong, “Fabrication and
Characterization of Carbon Nanotube Interconnects,” IEEE International Electron
Devices Meeting (IEDM), pp. 203 - 206, December 10 – 12, Washington, D.C.,
2007.
9. Y. Zhang, S.
Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, “An Integrated Phase
Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory,” Symp. VLSI
Technology, pp. 98 – 99, June 12 – 14, 2007, Kyoto, Japan.
Selected Recent
Publications:
1. G.F. Close, S. Yasuda, B. Paul, S. Fujita, H.-S. P. Wong, “1-GHz Integrated Circuit With Carbon Nanotube Interconnects and Silicon Transistors,” Nano Letters, Vol. 8, No. 2, pp. 706 – 709, February 13, 2008.
2. D. Akinwande, Y. Nishi, H.-S. P. Wong, “An Analytical Derivation of the Density of States, Effective Mass and Carrier Density for Achiral Carbon Nanotubes,” IEEE Trans. Electron Devices, vol. 55, No. 1, pp. 289 – 297, January, 2008.
3. K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauan, G. C. Wan, A. M. Ionescu, R.T. Howe, and H.S.-P. Wong, “Analytical Modeling of the Suspended-Gate FET and Design Insights for Low Power Logic,” IEEE Trans. Electron Devices, vol. 55, No. 1, pp. 48 – 59, January, 2008.
4. J. Deng, H.-S. P. Wong, “A Compact SPICE Model for Carbon Nanotube Field Effect Transistors Including Non-Idealities and Its Application — Part II: Full Device Model and Circuits Performance Benchmarking” IEEE Trans. Electron Devices, vol. 54, No. 12, pp. 3195 – 3205, December, 2007.
5. J. Deng, H.-S. P. Wong, “A Compact SPICE Model for Carbon Nanotube Field Effect Transistors Including Non-Idealities and Its Application — Part I: Model of Intrinsic Channel Region,” IEEE Trans. Electron Devices, vol. 54, No. 12, pp. 3186 – 3194, December, 2007.
6. J. Deng, H.-S. P. Wong, “Modeling and Analysis of Planar Gate Capacitance for 1-D FET with Multiple Cylindrical Conducting Channels,” IEEE Trans. Electron Devices, vol. 54, No. 9, pp. 2377 – 2385, September 2007.
7. D. Milliron, M.A. Caldwell, H.-S. P. Wong, “Synthesis of Metal Chalcogenide Nanodot Arrays Using Block Copolymer-Derived Nanoreactors,” Nano Letters, Vol. 7, No. 11, pp. 3503 – 3507 (2007) (DOI: 10.1021/nl072109b September 28, 2007.)
8. J. Reifenberg, M.A. Panzer, K.E. Goodson, S. Kim, A.M. Gibby, Y. Zhang, S. Wong, H.-S. P. Wong, E. Pop, “Thickness and Stoichiometry Dependence of the Thermal Conductivity of GeSbTe Films,” Applied Physics Letters, Vol. 91, Issue 11, 111904, September 11, 2007.
9. S. Kim, H.-S. P. Wong, “Analysis of Temperature in Phase Change Memory Scaling,” IEEE Electron Device Letters, vol. 28, No. 8, pp. 697 – 699, August, 2007.
10. Y. Zhang, H.-S. P. Wong, S. Raoux, J.N. Cha, C.T. Rettner, L.E. Krupp, T. Topuria, D.J. Milliron, P.M. Rice, J.L. Jordan-Sweet, “Phase Change Nanodot Arrays Fabricated Using a Self-Assembly Diblock Copolymer Approach,” Applied Physics Letters, 91, 013104, July 2, 2007.
11. J. Deng, K. Kim, C.-T. Chuang, H.-S. P. Wong, “The Impact of Device Footprint Scaling on High Performance CMOS Logic Technology,” IEEE Trans. Electron Devices, Vol. 55, No. 5, pp. 1148-1155 (2007).
12. A. Hazeghi, T. Krishnamohan, H.-S. P. Wong, “Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling,“ IEEE Trans. Electron Devices, pp. 439 – 445, March (2007).
13. D. Akinwande, G.F. Close, H-.S. P. Wong, “Analysis of the Frequency Response of Carbon Nanotube Transistors,“ IEEE Trans. Nanotechnology, Vol. 5, No. 5, pp. 599 – 605 (2006).
14.
L.-W. Chang, H.-S. P. Wong, “Diblock Copolymer Directed Self-Assembly for CMOS
Device Fabrication,” SPIE 31st
International Symposium on Microlithography,
Selected Publications Prior to Joining Stanford:
1. T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, “The Road to the End of CMOS Scaling,” invited paper, IEEE Circuits and Devices Magazine, pp. 16 – 26, 2005.
2. H.-S. P. Wong, “Beyond the Conventional Transistor,” Solid State Electronics, vol. 49, pp. 755 – 762 (2005).
3. J. Kedzierski, M. Ieong, T. Kanarsky, Y. Zhang, H.-S. P. Wong, „Fabrication of Metal Gated FinFETs Through Complete Gate Silicidation with Ni,” IEEE Trans. Electron Devices, vol. 51, No. 12, pp. 2115 – 2120 (2004).
4. D.V. Singh, K.A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill, H.-S. P. Wong, “Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors,” IEEE Trans. Nanotechnology, vol. 3, no. 3, pp. 383 – 387 (2004).
5. H. Shang, K.-L. Lee, P. Kozlowski, C.D’Emic, I. Babich, E. Sikorski, M. Ieong, H.-S. P. Wong, K. Guarini, and W. Haensch, “Self-Aligned n-Channel Germanium MOSFETs with a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate,” IEEE Electron Device Letters, vol. 25, No. 3, pp. 135 – 137 (2004).
6. J. Kedzierski, M. Ieong, E. Nowak, T.S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, H.-S. P. Wong, “Extension and Source/Drain Design for High-Performance FinFET Devices,” IEEE Transactions on Electron Devices, vol. 50, No. 4, pp. 952 – 958, April, 2003.
7. H. Shang, H. Okorn-Schmidt, J. Ott, P. Kozlowski, S. Steen, E.C. Jones, H.-S. P. Wong, W. Haensch, “Electrical Characterization of Germanium p-Channel MOSFETs,” IEEE Electron Device Letters, vol. 24, No. 4, pp. 242-244, April, 2003.
8. X. Wang, H.-S. P. Wong, P. Oldiges and R.J. Miller, “Electrostatic Analysis of Carbon Nanotube Arrays,” 2003 IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Cambridge, MA, September 3 – 5, 2003.
9. H.-S. P. Wong, J.
Appenzeller, V. Derycke, R. Martel, S. Wind, Ph. Avouris, “Carbon Nanotube
Field Effect Transistors – Fabrication, Device Physics, and Circuit
Implications”, IEEE International Solid State Circuits Conference (ISSCC), p.
370 – 371, 2003.
10. H.-S. P. Wong, “Beyond the Conventional Transistor”, invited paper, IBM J. Research & Development, March/May, pp. 133-168, 2002.
11. J. Kedzierski, E. Nowak, Thomas Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K.-L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H.-S. P. Wong, M. Ieong, W. Haensch, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 247 – 250, 2002
12. Z. Ren, S. Hedge, B. Doris, P. Oldiges, T. Kanarsky, O. Dokumaci, M. Ieong, E. C. Jones, H.-S. P. Wong, “An Experimental Study on Electrostatics and Transport Issues of Ultra-Thin Body SOI pMOSFETs”, IEEE Electron Device Letters, Vol. 23, No. 10, pp. 609-611, October, 2002.
13. L.J. Huang, J.O.Chu, S. Goma, C.P. D’Emic, S. J. Koester, D. F. Canaperi, P. M. Mooney, S. A. Cordes, J. L. Speidell, R. M. Anderson, H.-S. P. Wong, “Electron and Hole Mobility Enhancement in Strained Silicon-On-Insulator by Wafer Bonding,” IEEE Trans. Electron Devices, Vol. 49, pp. 1566 – 1571, September, 2002.
14. B. Doris, M. Ieong, T. Kanarsky, Y. Zhang, R.A. Roy, O. Dokumaci, F.-F. Jamin, L. Shi , W. Natzle, H.-J. Huang, J. Mezzapelle, A. Mocuta, M. Gribelyuk , E.C. Jones, R.J. Miller, H.-S. P. Wong, and W. Haensch, “Extreme Scaling With Ultra-Thin Silicon Channel MOSFET’s (XFET)”, IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, pp. 267 – 270, 2002.
15. K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B.H. Lee, A. Mocuta, J. Welser, S.L. Cohen, M. Ieong, and H.-S. P. Wong, “Mobility Enhancement in Strained Si NMOSFETs with HfO2 Gate Dielectrics”, Symp. VLSI Technology, pp. 12-13, June, 2002.
16. R. Martel, H.-S. P. Wong, K. Chan, and Ph. Avouris, “Carbon Nanotube Field Effect Transistors for Logic Applications”, IEEE International Electron Devices Meeting (IEDM), Washington, D.C., pp. 159-162, 2001.
17. D.J. Frank, R. H. Dennard, E. J. Nowak, P.M. Solomon, Y. Taur, H.-S. P. Wong, “Device Scaling Limits of Si MOSFETs and Their Application Dependencies”, invited paper, IEEE Proceedings, Special Issue on The Limits of Semiconductor Technology, pp. 259-288, March, 2001.
18. H.-S. P. Wong, D.J. Frank, P.M. Solomon, H.-J. Wann, J. Welser, “Nanoscale CMOS'', IEEE Proceedings, invited paper, Special Issue on Quantum Devices and Applications, pp. 537-570, April, 1999.
Recent and Upcoming
Presentations:
1. H.-S. P. Wong, “The Future of CMOS Scaling – Device Footprint Scaling and Parasitics Engineering,” invited paper, 2008 International Conference on Solid State and Integrated Circuit Technology (ICSICT 2008), Beijing, China, October 20-23, 2008.
2. H.-S. P. Wong, “Recent Progress in Carbon Nanotube Electronics – Modeling, Materials, Devices, Circuits, and Interconnects,” invited paper, 2008 International Conference on Solid State Devices and Materials (SSDM 2008), Tsukuba International Congress Center (EPOCHAL TSUKUBA), Ibaraki, Japan, September 23 – 26, 2008.
3. H.-S. P. Wong, “Beyond CMOS Scaling – What’s Next?” Integrated System Center Summer School “Nanoelectronic Circuits and Tools”, Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland, July 14 – 18, 2008.
4. H.-S. P. Wong, “The Future of CMOS Scaling” Integrated System Center Summer School “Nanoelectronic Circuits and Tools”, Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland, July 14 – 18, 2008.
5. H.-S. P. Wong, “Emerging Memories,” MIGAS, International Summer School on Advanced Microelectronics, IMEP-LAHC, Minatec-Grenoble INP, Autrans, France, June 28 – July 4, 2008
6. H.-S. P. Wong, “Devices and Technologies Beyond Si CMOS,” invited tutorial, International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan, April 21 – 23, 2008.
Last modified:
September 23, 2008